Efficient and correct execution of parallel programs that share memory
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Formal specification of abstract memory models
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The SPARC architecture manual (version 9)
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An executable specification, analyzer and verifier for RMO (relaxed memory order)
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Simple, fast, and practical non-blocking and blocking concurrent queue algorithms
PODC '96 Proceedings of the fifteenth annual ACM symposium on Principles of distributed computing
Practical implementations of non-blocking synchronization primitives
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Eraser: a dynamic data race detector for multithreaded programs
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Type-based race detection for Java
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CIL: Intermediate Language and Tools for Analysis and Transformation of C Programs
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Even Better DCAS-Based Concurrent Deques
DISC '00 Proceedings of the 14th International Conference on Distributed Computing
Automatic fence insertion for shared memory multiprocessing
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Correction of a Memory Management Method for Lock-Free Data Structures
Correction of a Memory Management Method for Lock-Free Data Structures
Race checking by context inference
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Scalable lock-free dynamic memory allocation
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Fast and lock-free concurrent priority queues for multi-thread systems
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Types for safe locking: Static race detection for Java
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Proving correctness of highly-concurrent linearisable objects
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Effective static race detection for Java
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LOCKSMITH: context-sensitive correlation analysis for race detection
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On the effectiveness of speculative and selective memory fences
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Formal verification of a lazy concurrent list-based set algorithm
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Bounded model checking of concurrent data types on relaxed memory models: a case study
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Bounded model checking of concurrent programs
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Race directed random testing of concurrent programs
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Deriving linearizable fine-grained concurrent objects
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Model checking transactional memories
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Effective Program Verification for Relaxed Memory Models
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Efficient Modeling of Concurrent Systems in BMC
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Randomized active atomicity violation detection in concurrent programs
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Java memory model aware software validation
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On the verification problem for weak memory models
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Formalising java's data race free guarantee
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Line-up: a complete and automatic linearizability checker
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MemSAT: checking axiomatic specifications of memory models
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Staged concurrent program analysis
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Verifying concurrent programs against sequential specifications
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A verification-based approach to memory fence insertion in PSO memory systems
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MEMORAX, a precise and sound tool for automatic fence insertion under TSO
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Volition: scalable and precise sequential consistency violation detection
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Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically
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Scaling data race detection for partitioned global address space programs
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WeeFence: toward making fences free in TSO
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Partial orders for efficient bounded model checking of concurrent software
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Computer Science - Research and Development
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Concurrency libraries can facilitate the development of multi-threaded programs by providing concurrent implementations of familiar data types such as queues or sets. There exist many optimized algorithms that can achieve superior performance on multiprocessors by allowing concurrent data accesses without using locks. Unfortunately, such algorithms can harbor subtle concurrency bugs. Moreover, they requirememory ordering fences to function correctly on relaxed memory models. To address these difficulties, we propose a verification approach that can exhaustively check all concurrent executions of a given test program on a relaxed memory model and can verify that they are observationally equivalent to a sequential execution. Our CheckFence prototype automatically translates the C implementation code and the test program into a SAT formula, hands the latter to a standard SAT solver, and constructs counter example traces if there exist incorrect executions. Applying CheckFence to five previously published algorithms, we were able to (1) find several bugs (some not previously known), and (2) determine how to place memory ordering fences for relaxed memory models.