Algorithms for mutual exclusion
Algorithms for mutual exclusion
Reasoning about parallel architectures
Reasoning about parallel architectures
Formal specification of abstract memory models
Proceedings of the 1993 symposium on Research on integrated systems
Pattern languages of program design 3
An Executable Specification and Verifier for Relaxed Memory Order
IEEE Transactions on Computers - Special issue on cache memory and related problems
Model checking
Specifying multithreaded Java semantics for program verification
Proceedings of the 24th International Conference on Software Engineering
The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Journal of Automated Reasoning
Formal Methods in System Design
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
CheckFence: checking consistency of concurrent data types on relaxed memory models
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Bounded model checking of concurrent data types on relaxed memory models: a case study
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
A memory model sensitive checker for c#
FM'06 Proceedings of the 14th international conference on Formal Methods
JRF-E: using model checking to give advice on eliminating memory model-related bugs
Proceedings of the IEEE/ACM international conference on Automated software engineering
WOMM: a weak operational memory model
ISoLA'10 Proceedings of the 4th international conference on Leveraging applications of formal methods, verification, and validation - Volume Part I
Sound and complete monitoring of sequential consistency for relaxed memory models
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Partial-coherence abstractions for relaxed memory models
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Automatic inference of memory fences
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Testing concurrent programs on relaxed memory models
Proceedings of the 2011 International Symposium on Software Testing and Analysis
Verifying fence elimination optimisations
SAS'11 Proceedings of the 18th international conference on Static analysis
Dynamic synthesis for relaxed memory models
Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation
CompCertTSO: A Verified Compiler for Relaxed-Memory Concurrency
Journal of the ACM (JACM)
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Modern concurrent programming languages like C# and Java have a programming language level memory model, which captures the set of all allowed behaviors of programs on any implementation platform--uni- or multi-processor. Such a memory model is typically weaker than Sequential Consistency and allows reordering of operations within a program thread. Therefore, programs verified correct by assuming Sequential Consistency (that is, each thread proceeds in program order) may not behave correctly on certain platforms! One solution to this problem is to develop program checkers which are memory model sensitive. In this paper, we develop a bytecode level invariant checker for the programming language C#. Our checker identifies program states which are reached only because the C# memory model is more relaxed than Sequential Consistency. It employs partial order reduction strategies to speed up the search. These strategies are different from standard partial order reduction methods since our search also considers execution traces containing bytecode re-orderings. Furthermore, our checker identifies (a) operation re-orderings which cause undesirable states to be reached, and (b) simple program modifications--by inserting memory barrier operations--which prevent such undesirable re-orderings.