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Formal specification of abstract memory models
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The SPARC architecture manual (version 9)
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An executable specification, analyzer and verifier for RMO (relaxed memory order)
Proceedings of the seventh annual ACM symposium on Parallel algorithms and architectures
Dynamic partial-order reduction for model checking software
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CheckFence: checking consistency of concurrent data types on relaxed memory models
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Iterative context bounding for systematic testing of multithreaded programs
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
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Memory model sensitive bytecode verification
Formal Methods in System Design
Effective Program Verification for Relaxed Memory Models
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
On the verification problem for weak memory models
Proceedings of the 37th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
x86-TSO: a rigorous and usable programmer's model for x86 multiprocessors
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Adversarial memory for detecting destructive races
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A trace simplification technique for effective debugging of concurrent programs
Proceedings of the eighteenth ACM SIGSOFT international symposium on Foundations of software engineering
Generating litmus tests for contrasting memory consistency models
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
Testing concurrent programs on relaxed memory models
Proceedings of the 2011 International Symposium on Software Testing and Analysis
Deciding robustness against total store ordering
ICALP'11 Proceedings of the 38th international conference on Automata, languages and programming - Volume Part II
Counter-Example guided fence insertion under TSO
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Automatic inference of memory fences
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Automatic fence insertion in integer programs via predicate abstraction
SAS'12 Proceedings of the 19th international conference on Static Analysis
Checking and enforcing robustness against TSO
ESOP'13 Proceedings of the 22nd European conference on Programming Languages and Systems
A verification-based approach to memory fence insertion in PSO memory systems
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
Volition: scalable and precise sequential consistency violation detection
Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems
Vulcan: Hardware Support for Detecting Sequential Consistency Violations Dynamically
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
WeeFence: toward making fences free in TSO
Proceedings of the 40th Annual International Symposium on Computer Architecture
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We present a technique for verifying that a program has no executions violating sequential consistency (SC) when run under the relaxed memory models Total Store Order (TSO) and Partial Store Order (PSO). The technique works by monitoring sequentially consistent executions of a program to detect if similar program executions could fail to be sequentially consistent under TSO or PSO.We propose novel monitoring algorithms that are sound and complete for TSO and PSO--if a program can exhibit an SC violation under TSO or PSO, then the corresponding monitor can detect this on some SC execution. The monitoring algorithms arise naturally from the operational definitions of these relaxed memory models, highlighting an advantage of viewing relaxed memory models operationally rather than axiomatically. We apply our technique to several concurrent data structures and synchronization primitives, detecting a number of violations of sequential consistency.