The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
An Executable Specification and Verifier for Relaxed Memory Order
IEEE Transactions on Computers - Special issue on cache memory and related problems
Communication and Concurrency
A Unified Formalization of Four Shared-Memory Models
IEEE Transactions on Parallel and Distributed Systems
Memory Consistency Models for Shared-Memory Multiprocessors
Memory Consistency Models for Shared-Memory Multiprocessors
Memory consistency models for high-performance distributed computing
Memory consistency models for high-performance distributed computing
Memory consistency models for high-performance distributed computing
Memory consistency models for high-performance distributed computing
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model
Proceedings of the 31st annual international symposium on Computer architecture
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
Foundations of the C++ concurrency memory model
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
The semantics of x86-CC multiprocessor machine code
Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Relaxed memory models: an operational approach
Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Formalising java's data race free guarantee
TPHOLs'07 Proceedings of the 20th international conference on Theorem proving in higher order logics
Reasoning about the implementation of concurrency abstractions on x86-TSO
ECOOP'10 Proceedings of the 24th European conference on Object-oriented programming
Fast and generalized polynomial time memory consistency verification
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Memory, an elusive abstraction
Proceedings of the 2010 international symposium on Memory management
Relaxed-memory concurrency and verified compilation
Proceedings of the 38th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Proceedings of the 38th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
ESOP'11/ETAPS'11 Proceedings of the 20th European conference on Programming languages and systems: part of the joint European conferences on theory and practice of software
Sound and complete monitoring of sequential consistency for relaxed memory models
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Litmus: running tests against hardware
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Performance implications of fence-based memory models
Proceedings of the 2011 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness
Understanding POWER multiprocessors
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
How to miscompile programs with "benign" data races
HotPar'11 Proceedings of the 3rd USENIX conference on Hot topic in parallelism
Testing concurrent programs on relaxed memory models
Proceedings of the 2011 International Symposium on Software Testing and Analysis
A verification-based approach to memory fence insertion in relaxed memory systems
Proceedings of the 18th international SPIN conference on Model checking software
Verifying fence elimination optimisations
SAS'11 Proceedings of the 18th international conference on Static analysis
Places: adding message-passing parallelism to racket
Proceedings of the 7th symposium on Dynamic languages
Clarifying and compiling C/C++ concurrency: from C++11 to POWER
POPL '12 Proceedings of the 39th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Efficient sequential consistency via conflict ordering
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Soundness of data flow analyses for weak memory models
APLAS'11 Proceedings of the 9th Asian conference on Programming Languages and Systems
Fences in weak memory models (extended version)
Formal Methods in System Design
Can seqlocks get along with programming language memory models?
Proceedings of the 2012 ACM SIGPLAN Workshop on Memory Systems Performance and Correctness
RockSalt: better, faster, stronger SFI for the x86
Proceedings of the 33rd ACM SIGPLAN conference on Programming Language Design and Implementation
What's decidable about weak memory models?
ESOP'12 Proceedings of the 21st European conference on Programming Languages and Systems
Java and the java memory model -- a unified, machine-checked formalisation
ESOP'12 Proceedings of the 21st European conference on Programming Languages and Systems
FOSSACS'12 Proceedings of the 15th international conference on Foundations of Software Science and Computational Structures
Counter-Example guided fence insertion under TSO
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
SALSA: scalable and low synchronization NUMA-aware algorithm for producer-consumer pools
Proceedings of the twenty-fourth annual ACM symposium on Parallelism in algorithms and architectures
False concurrency and strange-but-true machines
CONCUR'12 Proceedings of the 23rd international conference on Concurrency Theory
Position paper: nondeterminism is unavoidable, but data races are pure evil
Proceedings of the 2012 ACM workshop on Relaxing synchronization for multicore and manycore scalability
Automatic fence insertion in integer programs via predicate abstraction
SAS'12 Proceedings of the 19th international conference on Static Analysis
Plan B: a buffered memory model for Java
POPL '13 Proceedings of the 40th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Correct and efficient work-stealing for weak memory models
Proceedings of the 18th ACM SIGPLAN symposium on Principles and practice of parallel programming
Fast concurrent queues for x86 processors
Proceedings of the 18th ACM SIGPLAN symposium on Principles and practice of parallel programming
Quarantining weakness: compositional reasoning under relaxed memory models
ESOP'13 Proceedings of the 22nd European conference on Programming Languages and Systems
Checking and enforcing robustness against TSO
ESOP'13 Proceedings of the 22nd European conference on Programming Languages and Systems
A verification-based approach to memory fence insertion in PSO memory systems
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
An O(1)-barriers optimal RMRs mutual exclusion algorithm: extended abstract
Proceedings of the 2013 ACM symposium on Principles of distributed computing
Exploring memory consistency for massively-threaded throughput-oriented processors
Proceedings of the 40th Annual International Symposium on Computer Architecture
WeeFence: toward making fences free in TSO
Proceedings of the 40th Annual International Symposium on Computer Architecture
CompCertTSO: A Verified Compiler for Relaxed-Memory Concurrency
Journal of the ACM (JACM)
Location-aware cache management for many-core processors with deep cache hierarchy
SC '13 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
Making the java memory model safe
ACM Transactions on Programming Languages and Systems (TOPLAS)
Fence-free work stealing on bounded TSO processors
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
Hi-index | 48.22 |
Exploiting the multiprocessors that have recently become ubiquitous requires high-performance and reliable concurrent systems code, for concurrent data structures, operating system kernels, synchronization libraries, compilers, and so on. However, concurrent programming, which is always challenging, is made much more so by two problems. First, real multiprocessors typically do not provide the sequentially consistent memory that is assumed by most work on semantics and verification. Instead, they have relaxed memory models, varying in subtle ways between processor families, in which different hardware threads may have only loosely consistent views of a shared memory. Second, the public vendor architectures, supposedly specifying what programmers can rely on, are often in ambiguous informal prose (a particularly poor medium for loose specifications), leading to widespread confusion. In this paper we focus on x86 processors. We review several recent Intel and AMD specifications, showing that all contain serious ambiguities, some are arguably too weak to program above, and some are simply unsound with respect to actual hardware. We present a new x86-TSO programmer's model that, to the best of our knowledge, suffers from none of these problems. It is mathematically precise (rigorously defined in HOL4) but can be presented as an intuitive abstract machine which should be widely accessible to working programmers. We illustrate how this can be used to reason about the correctness of a Linux spinlock implementation and describe a general theory of data-race freedom for x86-TSO. This should put x86 multiprocessor system building on a more solid foundation; it should also provide a basis for future work on verification of such systems.