Two algorithms for barrier synchronization
International Journal of Parallel Programming
Algorithms for scalable synchronization on shared-memory multiprocessors
ACM Transactions on Computer Systems (TOCS)
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
A new solution of Dijkstra's concurrent programming problem
Communications of the ACM
Queue Locks on Cache Coherent Multiprocessors
Proceedings of the 8th International Symposium on Parallel Processing
Automatic fence insertion for shared memory multiprocessing
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
General decidability theorems for infinite-state systems
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
DISTRIBUTED ALGORITHMS , Lecture Notes for 6.852 FALL 1992
DISTRIBUTED ALGORITHMS , Lecture Notes for 6.852 FALL 1992
CheckFence: checking consistency of concurrent data types on relaxed memory models
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Effective Program Verification for Relaxed Memory Models
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
A Better x86 Memory Model: x86-TSO
TPHOLs '09 Proceedings of the 22nd International Conference on Theorem Proving in Higher Order Logics
On the verification problem for weak memory models
Proceedings of the 37th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
x86-TSO: a rigorous and usable programmer's model for x86 multiprocessors
Communications of the ACM
Reasoning about the implementation of concurrency abstractions on x86-TSO
ECOOP'10 Proceedings of the 24th European conference on Object-oriented programming
An automata-based symbolic approach for verifying programs on relaxed memory models
SPIN'10 Proceedings of the 17th international SPIN conference on Model checking software
Sound and complete monitoring of sequential consistency for relaxed memory models
TACAS'11/ETAPS'11 Proceedings of the 17th international conference on Tools and algorithms for the construction and analysis of systems: part of the joint European conferences on theory and practice of software
Partial-coherence abstractions for relaxed memory models
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Automatic inference of memory fences
Proceedings of the 2010 Conference on Formal Methods in Computer-Aided Design
Stability in weak memory models
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
Getting rid of store-buffers in TSO analysis
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
A verification-based approach to memory fence insertion in relaxed memory systems
Proceedings of the 18th international SPIN conference on Model checking software
Bounded model checking of concurrent data types on relaxed memory models: a case study
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
A memory model sensitive checker for c#
FM'06 Proceedings of the 14th international conference on Formal Methods
Automatic fence insertion in integer programs via predicate abstraction
SAS'12 Proceedings of the 19th international conference on Static Analysis
Software verification for weak memory via program transformation
ESOP'13 Proceedings of the 22nd European conference on Programming Languages and Systems
Checking and enforcing robustness against TSO
ESOP'13 Proceedings of the 22nd European conference on Programming Languages and Systems
A verification-based approach to memory fence insertion in PSO memory systems
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
MEMORAX, a precise and sound tool for automatic fence insertion under TSO
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
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We give a sound and complete fence insertion procedure for concurrent finite-state programs running under the classical TSO memory model. This model allows "write to read" relaxation corresponding to the addition of an unbounded store buffer between each processor and the main memory. We introduce a novel machine model, called the Single-Buffer (SB) semantics, and show that the reachability problem for a program under TSO can be reduced to the reachability problem under SB. We present a simple and effective backward reachability analysis algorithm for the latter, and propose a counter-example guided fence insertion procedure. The procedure is augmented by a placement constraint that allows the user to choose places inside the program where fences may be inserted. For a given placement constraint, we automatically infer all minimal sets of fences that ensure correctness. We have implemented a prototype and run it successfully on all standard benchmarks together with several challenging examples that are beyond the applicability of existing methods.