Efficient and correct execution of parallel programs that share memory
ACM Transactions on Programming Languages and Systems (TOPLAS)
The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Accommodating interference in the formal design of concurrent object-based programs
Formal Methods in System Design
Pattern languages of program design 3
An Executable Specification and Verifier for Relaxed Memory Order
IEEE Transactions on Computers - Special issue on cache memory and related problems
A Unified Formalization of Four Shared-Memory Models
IEEE Transactions on Parallel and Distributed Systems
Automated Software Engineering
Memory consistency models for high-performance distributed computing
Memory consistency models for high-performance distributed computing
Memory consistency models for high-performance distributed computing
Memory consistency models for high-performance distributed computing
Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming
A semantics for concurrent separation logic
Theoretical Computer Science
Resources, concurrency, and local reasoning
Theoretical Computer Science
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
Foundations of the C++ concurrency memory model
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Effective Program Verification for Relaxed Memory Models
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
On Validity of Program Transformations in the Java Memory Model
ECOOP '08 Proceedings of the 22nd European conference on Object-Oriented Programming
The semantics of x86-CC multiprocessor machine code
Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Relaxed memory models: an operational approach
Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
A Better x86 Memory Model: x86-TSO
TPHOLs '09 Proceedings of the 22nd International Conference on Theorem Proving in Higher Order Logics
Formalising java's data race free guarantee
TPHOLs'07 Proceedings of the 20th international conference on Theorem proving in higher order logics
x86-TSO: a rigorous and usable programmer's model for x86 multiprocessors
Communications of the ACM
A rely-guarantee proof system for x86-TSO
VSTTE'10 Proceedings of the Third international conference on Verified software: theories, tools, experiments
Relaxed-memory concurrency and verified compilation
Proceedings of the 38th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Proceedings of the 38th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Partial-coherence abstractions for relaxed memory models
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Deciding robustness against total store ordering
ICALP'11 Proceedings of the 38th international conference on Automata, languages and programming - Volume Part II
Stability in weak memory models
CAV'11 Proceedings of the 23rd international conference on Computer aided verification
A verification-based approach to memory fence insertion in relaxed memory systems
Proceedings of the 18th international SPIN conference on Model checking software
From total store order to sequential consistency: a practical reduction theorem
ITP'10 Proceedings of the First international conference on Interactive Theorem Proving
What's decidable about weak memory models?
ESOP'12 Proceedings of the 21st European conference on Programming Languages and Systems
Concurrent library correctness on the TSO memory model
ESOP'12 Proceedings of the 21st European conference on Programming Languages and Systems
Counter-Example guided fence insertion under TSO
TACAS'12 Proceedings of the 18th international conference on Tools and Algorithms for the Construction and Analysis of Systems
False concurrency and strange-but-true machines
CONCUR'12 Proceedings of the 23rd international conference on Concurrency Theory
Show no weakness: sequentially consistent specifications of TSO libraries
DISC'12 Proceedings of the 26th international conference on Distributed Computing
Quarantining weakness: compositional reasoning under relaxed memory models
ESOP'13 Proceedings of the 22nd European conference on Programming Languages and Systems
Software verification for weak memory via program transformation
ESOP'13 Proceedings of the 22nd European conference on Programming Languages and Systems
Checking and enforcing robustness against TSO
ESOP'13 Proceedings of the 22nd European conference on Programming Languages and Systems
MEMORAX, a precise and sound tool for automatic fence insertion under TSO
TACAS'13 Proceedings of the 19th international conference on Tools and Algorithms for the Construction and Analysis of Systems
CompCertTSO: A Verified Compiler for Relaxed-Memory Concurrency
Journal of the ACM (JACM)
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With the rise of multi-core processors, shared-memory concurrency has become a widespread feature of computation, from hardware, to operating systems, to programming languages such as C++ and Java. However, none of these provide sequentially consistent shared memory; instead they have relaxed memory models, which make concurrent programs even more challenging to understand. Programming language implementations run on hardware memory models, so VM and run-time system implementors must reason at both levels. Of particular interest are the low-level implementations of the abstractions that support language-level concurrency-especially because they invariably contain data races. In this paper, we develop a novel principle for reasoning about assembly programs on our previous x86-TSO memory model, and we use it to analyze five concurrency abstraction implementations: two spinlocks (from Linux); a non-blocking write protocol; the double-checked locking idiom; and java.util.concurrent's Parker. Our principle, called triangular-race freedom, strengthens the usual data-race freedom style of reasoning.