Memory access buffering in multiprocessors
ISCA '86 Proceedings of the 13th annual international symposium on Computer architecture
Proving sequential consistency of high-performance shared memories (extended abstract)
SPAA '91 Proceedings of the third annual ACM symposium on Parallel algorithms and architectures
Flow models of distributed computations: three equivalent semantics for CCS
Information and Computation
Designing memory consistency models for shared-memory multiprocessors
Designing memory consistency models for shared-memory multiprocessors
Commit-reconcile & fences (CRF): a new memory model for architects and compiler writers
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Minimal and Optimal Computations of Recursive Programs
Journal of the ACM (JACM)
Weak ordering—a new definition
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Memory consistency and event ordering in scalable shared-memory multiprocessors
ISCA '90 Proceedings of the 17th annual international symposium on Computer Architecture
Location Consistency-A New Memory Model and Cache Consistency Protocol
IEEE Transactions on Computers
Time, clocks, and the ordering of events in a distributed system
Communications of the ACM
On the Importance of an End-To-End View of Memory Consistency in Future Computer Systems
ISHPC '97 Proceedings of the International Symposium on High Performance Computing
A unified theory of shared memory consistency
Journal of the ACM (JACM)
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
What do high-level memory models mean for transactions?
Proceedings of the 2006 workshop on Memory system performance and correctness
Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming
Subtleties of Transactional Memory Atomicity Semantics
IEEE Computer Architecture Letters
How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
High-level small-step operational semantics for transactions
Proceedings of the 35th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Semantics of transactional memory and automatic mutual exclusion
Proceedings of the 35th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Foundations of the C++ concurrency memory model
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Proceedings of the 13th ACM SIGPLAN international conference on Functional programming
The java memory model: operationally, denotationally, axiomatically
ESOP'07 Proceedings of the 16th European conference on Programming
Formalising java's data race free guarantee
TPHOLs'07 Proceedings of the 20th international conference on Theorem proving in higher order logics
Oracle semantics for concurrent separation logic
ESOP'08/ETAPS'08 Proceedings of the Theory and practice of software, 17th European conference on Programming languages and systems
Toward a grainless semantics for shared-variable concurrency
FSTTCS'04 Proceedings of the 24th international conference on Foundations of Software Technology and Theoretical Computer Science
A Better x86 Memory Model: x86-TSO
TPHOLs '09 Proceedings of the 22nd International Conference on Theorem Proving in Higher Order Logics
x86-TSO: a rigorous and usable programmer's model for x86 multiprocessors
Communications of the ACM
Adversarial memory for detecting destructive races
PLDI '10 Proceedings of the 2010 ACM SIGPLAN conference on Programming language design and implementation
Proceedings of the twenty-second annual ACM symposium on Parallelism in algorithms and architectures
Reasoning about the implementation of concurrency abstractions on x86-TSO
ECOOP'10 Proceedings of the 24th European conference on Object-oriented programming
Typed assembly language for implementing OS kernels in SMP/multi-core environments with interrupts
SSV'10 Proceedings of the 5th international conference on Systems software verification
WOMM: a weak operational memory model
ISoLA'10 Proceedings of the 4th international conference on Leveraging applications of formal methods, verification, and validation - Volume Part I
ESOP'11/ETAPS'11 Proceedings of the 20th European conference on Programming languages and systems: part of the joint European conferences on theory and practice of software
Safe optimisations for shared-memory concurrent programs
Proceedings of the 32nd ACM SIGPLAN conference on Programming language design and implementation
Verification of STM on relaxed memory models
Formal Methods in System Design
Types for relaxed memory models
TLDI '12 Proceedings of the 8th ACM SIGPLAN workshop on Types in language design and implementation
Verifying local transformations on relaxed memory models
CC'10/ETAPS'10 Proceedings of the 19th joint European conference on Theory and Practice of Software, international conference on Compiler Construction
A theory of speculative computation
ESOP'10 Proceedings of the 19th European conference on Programming Languages and Systems
Parameterized memory models and concurrent separation logic
ESOP'10 Proceedings of the 19th European conference on Programming Languages and Systems
Generative operational semantics for relaxed memory models
ESOP'10 Proceedings of the 19th European conference on Programming Languages and Systems
FOSSACS'12 Proceedings of the 15th international conference on Foundations of Software Science and Computational Structures
A formal hierarchy of weak memory models
Formal Methods in System Design
Plan B: a buffered memory model for Java
POPL '13 Proceedings of the 40th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Making the java memory model safe
ACM Transactions on Programming Languages and Systems (TOPLAS)
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Memory models define an interface between programs written in some language and their implementation, determining which behaviour the memory (and thus a program) is allowed to have in a given model. A minimal guarantee memory models should provide to the programmer is that well-synchronized, that is, data-race free code has a standard semantics. Traditionally, memory models are defined axiomatically, setting constraints on the order in which memory operations are allowed to occur, and the programming language semantics is implicit as determining some of these constraints. In this work we propose a new approach to formalizing a memory model in which the model itself is part of a weak operational semantics for a (possibly concurrent) programming language. We formalize in this way a model that allows write operations to the store to be buffered. This enables us to derive the ordering constraints from the weak semantics of programs, and to prove, at the programming language level, that the weak semantics implements the usual interleaving semantics for data-race free programs, hence in particular that it implements the usual semantics for sequential code.