Alpha architecture reference manual
Alpha architecture reference manual
Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
Proceedings of the fourteenth annual ACM symposium on Principles of distributed computing
IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
The serializability of concurrent database updates
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Hiding Relaxed Memory Consistency with a Compiler
IEEE Transactions on Computers - Special issue on the parallel architecture and compilation techniques conference
Automatic fence insertion for shared memory multiprocessing
ICS '03 Proceedings of the 17th annual international conference on Supercomputing
Software transactional memory for dynamic-sized data structures
Proceedings of the twenty-second annual symposium on Principles of distributed computing
Atomizer: a dynamic atomicity checker for multithreaded programs
Proceedings of the 31st ACM SIGPLAN-SIGACT symposium on Principles of programming languages
KISS: keep it simple and sequential
Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation
Proceedings of the 32nd ACM SIGPLAN-SIGACT symposium on Principles of programming languages
VYRD: verifYing concurrent programs by runtime refinement-violation detection
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Proving correctness of highly-concurrent linearisable objects
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming
Testing implementations of transactional memory
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Proceedings of the 12th ACM SIGPLAN symposium on Principles and practice of parallel programming
CheckFence: checking consistency of concurrent data types on relaxed memory models
Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementation
Goldilocks: a race and transaction-aware java runtime
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How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs
IEEE Transactions on Computers
On the correctness of transactional memory
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming
Foundations of the C++ concurrency memory model
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Velodrome: a sound and complete dynamic atomicity checker for multithreaded programs
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Model checking transactional memories
Proceedings of the 2008 ACM SIGPLAN conference on Programming language design and implementation
Mechanical Verification of Transactional Memories with Non-transactional Memory Accesses
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Completeness and Nondeterminism in Model Checking Transactional Memories
CONCUR '08 Proceedings of the 19th international conference on Concurrency Theory
The semantics of x86-CC multiprocessor machine code
Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Relaxed memory models: an operational approach
Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principles of programming languages
FastTrack: efficient and precise dynamic race detection
Proceedings of the 2009 ACM SIGPLAN conference on Programming language design and implementation
Software Transactional Memory on Relaxed Memory Models
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Finding and reproducing Heisenbugs in concurrent programs
OSDI'08 Proceedings of the 8th USENIX conference on Operating systems design and implementation
Antichains: a new algorithm for checking universality of finite automata
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Formal verification of a lazy concurrent list-based set algorithm
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Bounded model checking of concurrent data types on relaxed memory models: a case study
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
DISC'06 Proceedings of the 20th international conference on Distributed Computing
Context-Bounded model checking of concurrent software
TACAS'05 Proceedings of the 11th international conference on Tools and Algorithms for the Construction and Analysis of Systems
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Software transactional memories (STM) are described in the literature with assumptions of sequentially consistent program execution and atomicity of high level operations like read, write, and abort. However, in a realistic setting, processors use relaxed memory models to optimize hardware performance. Moreover, the atomicity of operations depends on the underlying hardware. This paper presents the first approach to verify STMs under relaxed memory models with atomicity of 32 bit loads and stores, and read-modify-write operations. We describe RML, a simple language for expressing concurrent programs. We develop a semantics of RML parametrized by a relaxed memory model. We then present our tool, FOIL, which takes as input the RML description of an STM algorithm restricted to two threads and two variables, and the description of a memory model, and automatically determines the locations of fences, which if inserted, ensure the correctness of the restricted STM algorithm under the given memory model. We use FOIL to verify DSTM, TL2, and McRT STM under the memory models of sequential consistency, total store order, partial store order, and relaxed memory order for two threads and two variables. Finally, we extend the verification results for DSTM and TL2 to an arbitrary number of threads and variables by manually proving that the structural properties of STMs are satisfied at the hardware level of atomicity under the considered relaxed memory models.