Detecting data races on weak memory systems
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
Transactional memory: architectural support for lock-free data structures
ISCA '93 Proceedings of the 20th annual international symposium on computer architecture
Proceedings of the fourteenth annual ACM symposium on Principles of distributed computing
SIAM Journal on Computing
DAC '98 Proceedings of the 35th annual Design Automation Conference
The serializability of concurrent database updates
Journal of the ACM (JACM)
Verification of the UltraSPARC microprocessor
COMPCON '95 Proceedings of the 40th IEEE Computer Society International Conference
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model
Proceedings of the 31st annual international symposium on Computer architecture
Transactional Memory Coherence and Consistency
Proceedings of the 31st annual international symposium on Computer architecture
Programming with transactional coherence and consistency (TCC)
ASPLOS XI Proceedings of the 11th international conference on Architectural support for programming languages and operating systems
Unbounded Transactional Memory
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
A serializability violation detector for shared-memory server programs
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Virtualizing Transactional Memory
Proceedings of the 32nd annual international symposium on Computer Architecture
Efficient algorithms for verifying memory consistency
Proceedings of the seventeenth annual ACM symposium on Parallelism in algorithms and architectures
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor systems
IBM Journal of Research and Development
Testing patterns for software transactional memory engines
Proceedings of the 2007 ACM workshop on Parallel and distributed systems: testing and debugging
An Abort-Aware Model of Transactional Programming
VMCAI '09 Proceedings of the 10th International Conference on Verification, Model Checking, and Abstract Interpretation
Early experience with a commercial hardware transactional memory implementation
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Software Transactional Memory on Relaxed Memory Models
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Early experience with a commercial hardware transactional memory implementation
Early experience with a commercial hardware transactional memory implementation
Extensible transactional memory testbed
Journal of Parallel and Distributed Computing
Runtime verification for software transactional memories
RV'10 Proceedings of the First international conference on Runtime verification
Verification of STM on relaxed memory models
Formal Methods in System Design
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Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software. Given the subtle issues involved with concurrency and atomicity, however, it is important that transactional memory systems be carefully designed and aggressively tested to ensure their correctness. In this paper, we propose an axiomatic framework to model the formal specification of a realistic transactional memory system which may contain a mix of transactional and non-transactional operations. Using this framework and extensions to analysis algorithms originally developed for checking traditional memory consistency, we show that the widely practiced pseudo-random testing methodology can be effectively applied to transactional memory systems. Our testing methodology was successful in finding previously unknown bugs in the implementation of TCC, a transactional memory system. We study two flavors of the underlying analysis algorithm, one incomplete and the other complete, and show that the complete algorithm while being theoretically intractable is very efficient in practice.