Race-free interconnection networks and multiprocessor consistency
ISCA '91 Proceedings of the 18th annual international symposium on Computer architecture
The SPARC architecture manual (version 9)
The SPARC architecture manual (version 9)
On testing cache-coherent shared memories
SPAA '94 Proceedings of the sixth annual ACM symposium on Parallel algorithms and architectures
Time, clocks, and the ordering of events in a distributed system
Communications of the ACM
Automatable verification of sequential consistency
Proceedings of the thirteenth annual ACM symposium on Parallel algorithms and architectures
Verifying sequential consistency using vector clocks
Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures
Access Graphs: A Model for Investigating Memory Consistency
IEEE Transactions on Parallel and Distributed Systems
The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
The complexity of verifying memory coherence
Proceedings of the fifteenth annual ACM symposium on Parallel algorithms and architectures
Using Lamport Clocks to Reason About Relaxed Memory Models
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Constraint Graph Analysis of Multithreaded Programs
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model
Proceedings of the 31st annual international symposium on Computer architecture
A unified theory of shared memory consistency
Journal of the ACM (JACM)
Fundamentals of Distributed Computing: A Practical Tour of Vector Clock Systems
IEEE Distributed Systems Online
Testing implementations of transactional memory
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
A parametrized algorithm that implements sequential, causal, and cache memory consistencies
Journal of Systems and Software
Implementing sequentially consistent programs on processor consistent platforms
Journal of Parallel and Distributed Computing
Implied Set Closure and Its Application to Memory Consistency Verification
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Fast and generalized polynomial time memory consistency verification
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
On-the-fly verification of memory consistency with concurrent relaxed scoreboards
Proceedings of the Conference on Design, Automation and Test in Europe
On ESL verification of memory consistency for system-on-chip multiprocessing
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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One approach in verifying the correctness of a multiprocessor system is to show that its execution results comply with the memory consistency model it is meant to implement. It has been shown in prior work, however, that accurately verifying such compliance even of a single execution result is an NP-complete problem, for an unlimited number of processors. In this paper, we present a suite of post-mortem algorithms that perform the compliance check in an efficient, although not exhaustive, manner. Our algorithms employ the concept of vector clocks together with a heuristic made from a variation of the problem in P class. An implementation of these algorithms has been successful in efficiently detecting several bugs during the course of validating the design of commercial microprocessors and systems.Although our algorithms are presented with the Total Store Order (TSO) memory model, the ideas can also be applied to other models ranging from Sequential Consistency (SC) to a more relaxed one such as Relaxed Memory Order (RMO).