ACM Transactions on Programming Languages and Systems (TOPLAS)
SIAM Journal on Computing
Lamport clocks: verifying a directory cache-coherence protocol
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic
Logic of Programs, Workshop
Model-checking of correctness conditions for concurrent objects
LICS '96 Proceedings of the 11th Annual IEEE Symposium on Logic in Computer Science
Proving Sequential Consistency by Model Checking
Proving Sequential Consistency by Model Checking
Verifying sequential consistency using vector clocks
Proceedings of the fourteenth annual ACM symposium on Parallel algorithms and architectures
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Toward a decidable notion of sequential consistency
Proceedings of the fifteenth annual ACM symposium on Parallel algorithms and architectures
Verifying Sequential Consistency on Shared-Memory Multiprocessors by Model Checking
IEEE Transactions on Parallel and Distributed Systems
Memory Ordering: A Value-Based Approach
Proceedings of the 31st annual international symposium on Computer architecture
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model
Proceedings of the 31st annual international symposium on Computer architecture
Memory Ordering: A Value-Based Approach
IEEE Micro
The Complexity of Verifying Memory Coherence and Consistency
IEEE Transactions on Parallel and Distributed Systems
Efficient algorithms for verifying memory consistency
Proceedings of the seventeenth annual ACM symposium on Parallelism in algorithms and architectures
Memory Model = Instruction Reordering + Store Atomicity
Proceedings of the 33rd annual international symposium on Computer Architecture
Validating power architecture™ technology-based MPSoCs through executable specifications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Sequential consistency is a multiprocessor memory model of both practical and theoretical importance. Designing and implementing a memory system that efficiently provides a given memory model is a challenging and error-prone task, so automated verification support would be invaluable. Unfortunately, the general problem of deciding whether a finite-state protocol implements sequential consistency is undecidable. In this paper, we identify a restricted class of protocols for which verifying sequential consistency is decidable. The class includes all published sequentially consistent protocols that are known to us, and we argue why the class is likely to include all real sequentially consistent protocols. In principle, our method can be applied in a completely automated fashion for verification of all implemented protocols.