Formalization and Analysis of a Solution to the PCI 2.1 Bus Transaction Ordering Problem
Formal Methods in System Design - Special issue on formal methods for computer-added design
Automatable verification of sequential consistency
Proceedings of the thirteenth annual ACM symposium on Parallel algorithms and architectures
Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol
IEEE Transactions on Parallel and Distributed Systems
An Efficient Partial Order Reduction Algorithm with an Alternative Proviso Implementation
Formal Methods in System Design
A simulation-based method for the verification of shared memory in multiprocessor systems
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Verification Methods for Weaker Shared Memory Consistency Models
IPDPS '00 Proceedings of the 15 IPDPS 2000 Workshops on Parallel and Distributed Processing
Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
A Specification and Verification Framework for Developing Weak Shared Memory Consistency Protocols
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Verifying Sequential Consistency on Shared-Memory Multiprocessor Systems
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Toward a decidable notion of sequential consistency
Proceedings of the fifteenth annual ACM symposium on Parallel algorithms and architectures
Verifying Sequential Consistency on Shared-Memory Multiprocessors by Model Checking
IEEE Transactions on Parallel and Distributed Systems
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model
Proceedings of the 31st annual international symposium on Computer architecture
Efficient algorithms for verifying memory consistency
Proceedings of the seventeenth annual ACM symposium on Parallelism in algorithms and architectures
Memory model sensitive bytecode verification
Formal Methods in System Design
Validating power architecture™ technology-based MPSoCs through executable specifications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Toward reliable and efficient message passing software through formal analysis
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Generating litmus tests for contrasting memory consistency models
CAV'10 Proceedings of the 22nd international conference on Computer Aided Verification
A memory model sensitive checker for c#
FM'06 Proceedings of the 14th international conference on Formal Methods
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