Design and validation of computer protocols
Design and validation of computer protocols
Formal Verification for Fault-Tolerant Architectures: Prolegomena to the Design of PVS
IEEE Transactions on Software Engineering
A formal proof of absence of deadlock for any acyclic network of PCI buses
CHDL'97 Proceedings of the IFIP TC10 WG10.5 international conference on Hardware description languages and their applications : specification, modelling, verification and synthesis of microelectronic systems: specification, modelling, verification and synthesis of microelectronic systems
Using “test model-checking” to verify the Runway-PA8000 memory model
Proceedings of the tenth annual ACM symposium on Parallel algorithms and architectures
Formal modeling and validation applied to a commercial coherent bus: a case study
Proceedings of the IFIP WG 10.5 International Conference on Correct Hardware Design and Verification Methods: Advances in Hardware Design and Verification
The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
Protocol Verification by Aggregation of Distributed Transactions
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Verification of the Futurebus+ Cache Coherence Protocol
Verification of the Futurebus+ Cache Coherence Protocol
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Specification of an Asynchronous On-chip Bus
ICFEM '02 Proceedings of the 4th International Conference on Formal Engineering Methods: Formal Methods and Software Engineering
Routing Information Protocol in HOL/SPIN
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Formal Verification of the Alpha 21364 Network Protocol
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Incremental Proof of the Producer/Consumer Property for the PCI Protocol
ZB '02 Proceedings of the 2nd International Conference of B and Z Users on Formal Specification and Development in Z and B
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Evaluating reasoning heuristics in the context of multi-level marketing structures
SAICSIT '04 Proceedings of the 2004 annual research conference of the South African institute of computer scientists and information technologists on IT research in developing countries
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Incremental modelling and verification of the PCI express transaction layer
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Incremental and verified modeling of the PCI express protocol
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
| Hi-index | 0.00 |
The transaction ordering problem of the original PCI 2.1 standard busspecification violates the desired correctness property of maintainingthe so called ‘Producer/Consumer’ relationship between writers andreaders of data. This violation stems mainly from the so called completion stealing problem, first identified and solved by Corellaet al. [4], and supported by a formal paper andpencil argument. In this paper, we develop a flexible graph theorylibrary in PVS for modeling computer bus structures, formalize the PCI2.1 protocol containing the solution of [4] in it,and mechanically prove the absence of completion stealing. Next, wedefine the Producer/Consumer property in PVS and sketch its mechanicalproof. Noting the complexity of this proof effort (unfinished asyet), we explore a combination of theorem proving and model-checkingin which the model used for model-checking is made tractable byexploiting the formal theorems established during theorem-proving aswell as several intuitively justified assumptions. The theorem-proving infrastructure we have built for modelingCPU interconnect structures is highly reusable.Our work is one example of a natural division of labor betweentheorem-proving and model-checking in tackling system-levelverification problems under realistic time budgets.