Using belief to reason about cache coherence
PODC '94 Proceedings of the thirteenth annual ACM symposium on Principles of distributed computing
Formal verification of an IBM CoreConnect processor local bus arbiter core
Proceedings of the 37th Annual Design Automation Conference
Formalization and Analysis of a Solution to the PCI 2.1 Bus Transaction Ordering Problem
Formal Methods in System Design - Special issue on formal methods for computer-added design
Formal validation of virtual finite state machines
WIFT '95 Proceedings of the 1st Workshop on Industrial-Strength Formal Specification Techniques
Verification of AMBA Using a Combination of Model Checking and Theorem Proving
Electronic Notes in Theoretical Computer Science (ENTCS)
Formal verification and testing of protocols
Computer Communications
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We used a hardware description language to construct a formal model of the cache coherence protocol described in the draft IEEE Futurebus+ standard. By applying temporal logic model checking techniques, we found several errors in the standard. The result of our project is a concise, comprehensible and unambiguous model of the protocol that should be useful both to the Futurebus+ Working Group members, who are responsible for the protocol, and to actual designers of Futurebus+ boards.