Design and validation of computer protocols
Design and validation of computer protocols
A partial approach to model checking
Papers presented at the IEEE symposium on Logic in computer science
Protocol Verification as a Hardware Design Aid
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Proving the value of formal methods
Proceedings of the 7th IFIP WG6.1 International Conference on Formal Description Techniques VII
Formal Methods at AT&T - An Industrial Usage Report
FORTE '91 Proceedings of the IFIP TC6/WG6.1 Fourth International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols: Formal Description Techniques, IV
Combining Partial Order Reductions with On-the-fly Model-Checking
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Verification of the Futurebus+ Cache Coherence Protocol
Verification of the Futurebus+ Cache Coherence Protocol
Model checking software systems: a case study
SIGSOFT '95 Proceedings of the 3rd ACM SIGSOFT symposium on Foundations of software engineering
Using partial-order methods in the formal validation of industrial concurrent programs
ISSTA '96 Proceedings of the 1996 ACM SIGSOFT international symposium on Software testing and analysis
Using Partial-Order Methods in the Formal Validation of Industrial Concurrent Programs
IEEE Transactions on Software Engineering - Special issue: best papers of the 1996 international symposium on software testing and analysis ISSTA'96
Model checking for programming languages using VeriSoft
Proceedings of the 24th ACM SIGPLAN-SIGACT symposium on Principles of programming languages
Mawl: A Domain-Specific Language for Form-Based Services
IEEE Transactions on Software Engineering
Software model checking in practice: an industrial case study
Proceedings of the 24th International Conference on Software Engineering
Software Model Checking: The VeriSoft Approach
Formal Methods in System Design
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We describe our experiences in introducing a formal validation tool in several projects that are developing software for AT&T's 5ESS telephone switching system. The tool validates networks of communicating processes implemented in the virtual finite state machine (VFSM) notation, using Holzmann's (1991) super-trace algorithm to check for errors in process interaction such as deadlock, livelock, unexpected inputs, message buffer overflow, and unreachable code. The validator has been used by several 5ESS developers to find bugs in their VFSM designs. We discuss the extent to which the validator has been successfully employed in 5ESS software development, and describe our present research efforts to eliminate some of the roadblocks that stand in the way of its more widespread use.