An improved protocol reachability analysis technique
Software—Practice & Experience
Defining conditional independence using collapses
Theoretical Computer Science - Selected papers of the International BCS-FACS Workshop on Semantics for Concurrency, Leicester, UK, July 1990
Partial-Order Methods for Temporal Verification
CONCUR '93 Proceedings of the 4th International Conference on Concurrency Theory
On-the-Fly Verification with Stubborn Sets
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Refining Dependencies Improves Partial-Order Verification Methods (Extended Abstract)
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Combining Partial Order Reductions with On-the-fly Model-Checking
CAV '94 Proceedings of the 6th International Conference on Computer Aided Verification
Formal validation of virtual finite state machines
WIFT '95 Proceedings of the 1st Workshop on Industrial-Strength Formal Specification Techniques
Verification of concurrent systems: function and timing
Verification of concurrent systems: function and timing
Verification of distributed programs using representative interleaving sequences
Distributed Computing
Elements of Style: Analyzing a Software Design Feature with a Counterexample Detector
IEEE Transactions on Software Engineering - Special issue: best papers of the 1996 international symposium on software testing and analysis ISSTA'96
Using Partial-Order Methods in the Formal Validation of Industrial Concurrent Programs
IEEE Transactions on Software Engineering - Special issue: best papers of the 1996 international symposium on software testing and analysis ISSTA'96
Verifying security protocols with Brutus
ACM Transactions on Software Engineering and Methodology (TOSEM)
Partial Order Reductions for Security Protocol Verification
TACAS '00 Proceedings of the 6th International Conference on Tools and Algorithms for Construction and Analysis of Systems: Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000
Abstract BDDs: A Technque for Using Abstraction in Model Checking
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Counterexample-guided abstraction refinement for symbolic model checking
Journal of the ACM (JACM)
Partial order reduction for markov decision processes: a survey
FMCO'05 Proceedings of the 4th international conference on Formal Methods for Components and Objects
Protocol quality engineering: addressing industry concerns about formal methods
Computer Communications
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We have developed a formal validation tool that has been used on several projects that are developing software for AT&T's 5ESS™ telephone switching system. The tool uses Holzmann's supertrace algorithm to check for errors such as deadlock and livelock in networks of communicating processes. The validator invariably finds subtle errors that were missed during thorough simulation and testing; however, the brute-force search it performs can result in extremely long running times, which can be frustrating to users. Recently, a number of researchers have been investigating techniques known as partial-order methods that can significantly reduce the running time of formal validation by avoiding redundant exploration of execution scenarios. In this paper, we describe the design of a partial-order algorithm for our validation tool and discuss its effectiveness. We show that a careful compile-time static analysis of process communication behavior yields information that can be used during validation to dramatically improve its performance. We demonstrate the effectiveness of our partial-order algorithm by presenting the results of experiments with actual industrial examples drawn from a variety of 5ESS™ application domains, including call processing, signalling, and switch maintenance.