Formal verification and testing of protocols

  • Authors:
  • D. R. Avresky

  • Affiliations:
  • Department of Electrical Engineering, Boston University, 8 Saint Mary's Street, Boston, MA 02146, USA

  • Venue:
  • Computer Communications
  • Year:
  • 1999

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Abstract

We adopt a formalism to describe protocols that is close to the human way of thinking and can be easily used to perform reachability analysis of the described protocol in a state-transition format. This formalism allows for an execution tree (ET) to be generated from a set of assertions such that all paths from the root to the leaves are well-defined formulas. We then extend the formalism with regards to real-time properties. Finally, we present a software verification tool, that implements the aforementioned features in the analysis of protocols.