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ACM Transactions on Programming Languages and Systems (TOPLAS)
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Automatic synthesis of interfaces between incompatible protocols
DAC '98 Proceedings of the 35th annual Design Automation Conference
Model checking
Formalization and Analysis of a Solution to the PCI 2.1 Bus Transaction Ordering Problem
Formal Methods in System Design - Special issue on formal methods for computer-added design
High-Level specification and automatic generation of IP interface monitors
Proceedings of the 39th annual Design Automation Conference
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Directed-simulation assisted formal verification of serial protocol and bridge
Proceedings of the 43rd annual Design Automation Conference
Formal performance evaluation of AMBA-based system-on-chip designs
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
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ACL2 '06 Proceedings of the sixth international workshop on the ACL2 theorem prover and its applications
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Proceedings of the conference on Design, automation and test in Europe
Executable formal specification and validation of NoC communication infrastructures
Proceedings of the 21st annual symposium on Integrated circuits and system design
A refinement approach to design and verification of on-chip communication protocols
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
A formal approach to the verification of networks on chip
EURASIP Journal on Embedded Systems
Verification of AMBA Using a Combination of Model Checking and Theorem Proving
Electronic Notes in Theoretical Computer Science (ENTCS)
Incremental modelling and verification of the PCI express transaction layer
MEMOCODE'09 Proceedings of the 7th IEEE/ACM international conference on Formal Methods and Models for Codesign
Formal specification of networks-on-chips: deadlock and evacuation
Proceedings of the Conference on Design, Automation and Test in Europe
Incremental and verified modeling of the PCI express protocol
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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International Journal of Computer Applications in Technology
A generic network on chip model
TPHOLs'05 Proceedings of the 18th international conference on Theorem Proving in Higher Order Logics
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Proceedings of the International Conference on Advances in Computing, Communications and Informatics
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ICICA'12 Proceedings of the Third international conference on Information Computing and Applications
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System-on-chip (SoC) designs use bus protocols for high performance data transfer among the Intellectual Property (IP) cores. These protocols incorporate advanced features such as pipelining, burst and split transfers. In this paper, we describe a case study in formally verifying a widely used SoC bus protocol: the Advanced Micro-controller Bus Architecture (AMBA) protocol from ARM. In particular, we develop a formal specification of the AMBA protocol. We then employ model checking, a state space exploration based formal verification technique, to verify crucial design invariants. The presence of pipelining and split transfer in the AMBA protocol gives rise to interesting corner cases, which are hard to detect via informal reasoning. Using the SMV model checker, we have detected a potential bus starvation scenario in the AMBA protocol. Such scenarios demonstrate the inherent intricacies in designing pipelined bus protocols.