Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Automatic functional test generation using the extended finite state machine model
DAC '93 Proceedings of the 30th international Design Automation Conference
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
High-Level specification and automatic generation of IP interface monitors
Proceedings of the 39th annual Design Automation Conference
Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Optimization problems from feature testing of communication protocols
ICNP '96 Proceedings of the 1996 International Conference on Network Protocols (ICNP '96)
A Framework for Constrained Functional Verification
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient Generation of Monitor Circuits for GSTE Assertion Graphs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On compliance test of on-chip bus for SOC
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Proposal for Transaction-Level Verification with Component Wrapper Language
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Constraint-Based Verification
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Verifying if an integrated component is compliant with certain interface protocol is a vital issue in component-based system-on-a-chip (SoC) designs. For simulation-based verification, generating massive constrained simulation stimuli is becoming crucial to achieve a high verification quality. To further improve the quality, stimulus biasing techniques are often used to guide the simulation to hit design corners. In this paper, we model the interface protocol with the non-deterministic extended finite-state machine (NEFSM), and then propose an automatic stimulus generation approach based on it. This approach is capable of providing numerous biasing strategies. Experiment results demonstrate the high controllability and efficiency of our stimulus generation scheme.