System-on-a-chip verification: methodology and techniques
System-on-a-chip verification: methodology and techniques
Symbolic Model Checking
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
FSM-based transaction-level functional coverage for interface compliance verification
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
TCG inside?: a note on TPM specification compliance
Proceedings of the first ACM workshop on Scalable trusted computing
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Formal modeling and model checking analysis of the wishbone system-on-chip bus protocol
ICICA'12 Proceedings of the Third international conference on Information Computing and Applications
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In this paper, we employ a monitor-based approach for on-chip bus (OCB) compliance test. To describe the OCB protocols, we propose a FSM model, which can help to extract the necessary properties systematically and verify the data part of a bus transfer efficiently. To demonstrate our methodology, we illustrate two OCB protocols, WISHBONE and AMBA AHB, as the study cases. The experimental results show that we can verify the OCB protocols efficiently and detect the design errors when tests fail.