Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Counterexample-guided choice of projections in approximate symbolic model checking
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
Executable Protocol Specification in ESL
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Design Constraints in Symbolic Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
A Theory of Consistency for Modular Synchronous Systems
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Scalable hybrid verification of complex microprocessors
Proceedings of the 38th annual Design Automation Conference
SATIRE: a new incremental satisfiability engine
Proceedings of the 38th annual Design Automation Conference
High-Level specification and automatic generation of IP interface monitors
Proceedings of the 39th annual Design Automation Conference
Deriving a simulation input generator and a coverage metric from a formal specification
Proceedings of the 39th annual Design Automation Conference
Using Formal Specifications for Functional Validation of Hardware Designs
IEEE Design & Test
Executable Protocol Specification in ESL
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Incremental Proof of the Producer/Consumer Property for the PCI Protocol
ZB '02 Proceedings of the 2nd International Conference of B and Z Users on Formal Specification and Development in Z and B
A Theory of Consistency for Modular Synchronous Systems
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Convertibility verification and converter synthesis: two faces of the same coin
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Formal hardware specification languages for protocol compliance verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient Generation of Monitor Circuits for GSTE Assertion Graphs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
On compliance test of on-chip bus for SOC
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Using Formal Techniques to Debug the AMBA System-on-Chip Bus Protocol
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On the Design and Verification Methodology of the Look-Aside Interface
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
A Formal Framework for Modeling and Analysis of System-Level Dynamic Power Management
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
XFM: An incremental methodology for developing formal models
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Tightly integrate dynamic verification with formal verification: a GSTE based approach
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
XFM: extreme formal method for capturing formal specification into abstract models
Formal methods and models for system design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
BUSpec: A framework for generation of verification aids for standard bus protocol specifications
Integration, the VLSI Journal
Auxiliary state machines + context-triggered properties in verification
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analyzing the impact of protocol changes on tests
TestCom'06 Proceedings of the 18th IFIP TC6/WG6.1 international conference on Testing of Communicating Systems
An approach for the verification of systemc designs using asml
ATVA'05 Proceedings of the Third international conference on Automated Technology for Verification and Analysis
Runtime verification of microcontroller binary code
Science of Computer Programming
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Bus protocols are hard to specify correctly, and yet it is often critical and highly beneficial that their specifications are correct, complete, and unambiguous. The informal specifications currently in use are not adequate because they are difficult to read and write, and cannot be functionally verified by automated tools. Formal specifications, promise to eliminate these problems, but in practice, the difficulty of writing them limits their widespread acceptance. This paper presents a new style of specification based on writing the interface specification as a formal monitor, which enables the formal specification to be simple to write, and even allows the description to be written in existing HDLs. Despite the simplicity, monitor specifications can be used to specify industry-grade protocols. Furthermore, they can be checked automatically for internal consistency using standard model checker tools, without any protocol implementations. They can be used without modification for several other purposes, such as formal verification and system simulation of implementations. Additionally, it is proved that specifications written in this style are receptive, guaranteeing that implementations are possible. The effectiveness of the monitor specification is demonstrated by formally specifying a large subset of the PCI 2.2 standard and finding several bugs in the standard.