Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Coverage estimation for symbolic model checking
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Modeling design constraints and biasing in simulation using BDDs
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
High-Level specification and automatic generation of IP interface monitors
Proceedings of the 39th annual Design Automation Conference
Principles of Verifiable RTL Design
Principles of Verifiable RTL Design
A Methodology for Large-Scale Hardware Verification
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Monitor-Based Formal Specification of PCI
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Generalized Symbolic Trajectory Evaluation - Abstraction in Action
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Design Constraints in Symbolic Model Checking
CAV '98 Proceedings of the 10th International Conference on Computer Aided Verification
High level formal verification of next-generation microprocessors
Proceedings of the 40th annual Design Automation Conference
Introduction to Generalized Symbolic Trajectory Evaluation
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
High level validation of next-generation microprocessors
HLDVT '02 Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop
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GSTE (Generalized Symbolic Trajectory Evaluation) is a high capacity formal verification technology that has been successfully applied to verifying complex Intel designs with tens of thousands of state elements. In this paper, we extend the use of GSTE by developing a dynamic checker that verifies a GSTE specification against a scalar simulation trace. Unlike previous approaches, both the formal checker and the dynamic checker work directly on a GSTE specification without the need for an intermediate monitor circuit. Our approach also offers a straight forward way to measure the quality (coverage) of a specification. The dynamic checker has been used in the real-life micro-processor design verification.