Formally verifying a microprocessor using a simulation methodology
DAC '94 Proceedings of the 31st annual Design Automation Conference
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of content addressable memories using symbolic trajectory evaluation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Model checking
Proceedings of the 37th Annual Design Automation Conference
Symbolic Model Checking
Early Quantification and Partitioned Transition Relations
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
A Methodology for Large-Scale Hardware Verification
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Generalized Symbolic Trajectory Evaluation - Abstraction in Action
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
The Mathematical Foundation fo Symbolic Trajectory Evaluation
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Formal Verification of Digital Circuits Using Symbolic Ternary System Models
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
Verifying Temporal Properties of Sequential Machines Without Building their State Diagrams
CAV '90 Proceedings of the 2nd International Workshop on Computer Aided Verification
An Iterative Approach to Language Containment
CAV '93 Proceedings of the 5th International Conference on Computer Aided Verification
Introduction to Generalized Symbolic Trajectory Evaluation
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Formal hardware verification by symbolic trajectory evaluation
Formal hardware verification by symbolic trajectory evaluation
Introduction to generalized symbolic trajectory evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Exploiting symmetry when verifying transistor-level circuits by symbolic trajectory evaluation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A simple theorem prover based on symbolic trajectory evaluation and BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
LPAR '01 Proceedings of the Artificial Intelligence on Logic for Programming
Generalized Symbolic Trajectory Evaluation - Abstraction in Action
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
High level formal verification of next-generation microprocessors
Proceedings of the 40th annual Design Automation Conference
Introduction to generalized symbolic trajectory evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
A SAT-based algorithm for reparameterization in symbolic simulation
Proceedings of the 41st annual Design Automation Conference
Efficient Generation of Monitor Circuits for GSTE Assertion Graphs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
TheoSim: combining symbolic simulation and theorem proving for hardware verification
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Set Manipulation with Boolean Functional Vectors for Symbolic Reachability Analysis
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Verification of behavioral descriptions by combining symbolic simulation and automatic reasoning
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Tightly integrate dynamic verification with formal verification: a GSTE based approach
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
GSTE is partitioned model checking
Formal Methods in System Design
Property-driven partitioning for abstraction refinement
TACAS'07 Proceedings of the 13th international conference on Tools and algorithms for the construction and analysis of systems
Combining several paradigms for circuit validation and verification
CASSIS'04 Proceedings of the 2004 international conference on Construction and Analysis of Safe, Secure, and Interoperable Smart Devices
Automatic refinement and vacuity detection for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Symbolic systems, explicit properties: on hybrid approaches for LTL symbolic model checking
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
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Generalized STE (Symbolic Trajectory Evaluation) [21, 22, 23] is a very significant extension of STE [11, 20] that truly combines the efficiency, capacity and ease of use of STE with the ability of classic symbolic model checking for verifying a much richer set of properties [9]. GSTE provides a unified model checking framework that gives one the power to choose and seamlessly adjust the level of abstraction in a model as well as in a specification during a verification effort. This paper describes some of the techniques that made this possible using a simple FIFO example for illustration. Finally, a set of real life verification results is provided to strongly demonstrate the viability of GSTE as a new generation model checking solution for complex designs.