Linking BDD-based symbolic evaluation to interactive theorem-proving
DAC '93 Proceedings of the 30th international Design Automation Conference
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
The formal verification of a pipelined double-precision IEEE floating-point multiplier
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Formal verification of FIRE: a case study
DAC '97 Proceedings of the 34th annual Design Automation Conference
A Hybrid Approach to Verifying Liveness in a Symmetric Multi-Processor
TPHOLs '97 Proceedings of the 10th International Conference on Theorem Proving in Higher Order Logics
WIFT '95 Proceedings of the 1st Workshop on Industrial-Strength Formal Specification Techniques
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Formal verification of iterative algorithms in microprocessors
Proceedings of the 37th Annual Design Automation Conference
Practical Formal Verification in Microprocessor Design
IEEE Design & Test
A Methodology for Large-Scale Hardware Verification
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Sequential Equivalence Checking by Symbolic Simulation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Abstraction by Symbolic Indexing Transformations
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Generalized Symbolic Trajectory Evaluation - Abstraction in Action
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Reachability Programming in HOL98 Using BDDs
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
PROSPER - An Investigation into Software Architecture for Embedded Proof Engines
FroCoS '02 Proceedings of the 4th International Workshop on Frontiers of Combining Systems
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Introduction to generalized symbolic trajectory evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Efficient Generation of Monitor Circuits for GSTE Assertion Graphs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Encyclopedia of Computer Science
Simulation-based bug trace minimization with BMC-based refinement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Distance-guided hybrid verification with GUIDO
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A Survey of Hybrid Techniques for Functional Verification
IEEE Design & Test
An abstract reachability approach by combining HOL induction and multiway decision graphs
Journal of Computer Science and Technology
Debugging strategies for mere mortals
Proceedings of the 46th Annual Design Automation Conference
A novel formalization of symbolic trajectory evaluation semantics in Isabelle/HOL
Theoretical Computer Science
A monadic approach to automated reasoning for Bluespec SystemVerilog
Innovations in Systems and Software Engineering
Exploring structural symmetry automatically in symbolic trajectory evaluation
Formal Methods in System Design
On locally checkable properties
LPAR'06 Proceedings of the 13th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Maximal models of assertion graph in GSTE
TAMC'06 Proceedings of the Third international conference on Theory and Applications of Models of Computation
Combining theorem proving and symbolic trajectory evaluation in THM&STE
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
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We describe the verification of the IM: a large, complex (12,000gates and 1100 latches) circuit that detects and marks the boundariesbetween Intel architecture (IA-32) instructions. We verified agate-level model of the IM against an implementation-independentspecification of IA-32 instruction lengths. We used theorem provingto to derive 56 model-checking runs and to verify that the model-checkingruns imply that the IM meets the specification for all possiblesequences of IA-32 instructions. Our verification discoveredeight previously unknown bugs.