Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
A methodology for hardware verification based on logic simulation
Journal of the ACM (JACM)
Formal hardware verification by symbolic ternary trajectory evaluation
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Formal verification of content addressable memories using symbolic trajectory evaluation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Divider Circuit Verification with Model Checking and Theorem Proving
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
The Mathematical Foundation fo Symbolic Trajectory Evaluation
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Introduction to Generalized Symbolic Trajectory Evaluation
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Applications of symbolic simulation to the formal verification of microprocessors
Applications of symbolic simulation to the formal verification of microprocessors
Explaining symbolic trajectory evaluation by giving it a faithful semantics
CSR'06 Proceedings of the First international computer science conference on Theory and Applications
SAT-based assistance in abstraction refinement for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
An introduction to symbolic trajectory evaluation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
A mechanically verified AIG-to-BDD conversion algorithm
ITP'10 Proceedings of the First international conference on Interactive Theorem Proving
On model checking data-independent systems with arrays with whole-array operations
CSP'04 Proceedings of the 2004 international conference on Communicating Sequential Processes: the First 25 Years
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Symbolic indexing is a data abstraction technique that exploits the partially-ordered state space of symbolic trajectory evaluation (STE). Use of this technique has been somewhat limited in practice because of its complexity. We present logical machinery and efficient algorithms that provide a much simpler interface to symbolic indexing for the STE user. Our logical machinery also allows correctness assertions proved by symbolic indexing to be composed into larger properties, something previously not possible.