Programming: the derivation of algorithms
Programming: the derivation of algorithms
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
ML for the working programmer (2nd ed.)
ML for the working programmer (2nd ed.)
Word level model checking—avoiding the Pentium FDIV error
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Bit-level analysis of an SRT divider circuit
DAC '96 Proceedings of the 33rd annual Design Automation Conference
A Mechanically Checked Proof of the AMD5K86TM Floating-Point Division Program
IEEE Transactions on Computers
Formal verification of iterative algorithms in microprocessors
Proceedings of the 37th Annual Design Automation Conference
The Science of Programming
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Division and Square Root: Digit-Recurrence Algorithms and Implementations
Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking
FMCAD '96 Proceedings of the First International Conference on Formal Methods in Computer-Aided Design
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
A Machine-Checked Theory of Floating Point Arithmetic
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Verifying the SRT Division Algorithm Using Theorem Proving Techniques
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Symbolic Trajectory Evaluation
Formal Hardware Verification - Methods and Systems in Comparison
A Correctness Model for Pipelined Multiprocessors
TPCD '94 Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience
The Implementation of Functional Programming Languages (Prentice-Hall International Series in Computer Science)
A simple theorem prover based on symbolic trajectory evaluation and BDD's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Abstraction by Symbolic Indexing Transformations
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Proof Engineering in the Large: Formal Verification of Pentium® 4 Floating-Point Divider
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Theorem Proving for Verification (Invited Tutorial)
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
Efficient and accurate computation of upper bounds of approximation errors
Theoretical Computer Science
A monadic approach to automated reasoning for Bluespec SystemVerilog
Innovations in Systems and Software Engineering
Hybrid verification of a hardware modular reduction engine
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
Floating-Point verification using theorem proving
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
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Most industrial-size hardware verification problems are amenable to neither fully automated nor fully manual hardware verification methods. However, combinations of these two extremes, human-constructed proofs with automatically verified lower-level steps, seem to offer great promise. In this paper we discuss a formal verification case study based on such a combination of theorem-proving and model-checking techniques. The case study addresses the correctness of a floating-point divider unit of an Intel IA-32 microprocessor. The verification was carried out in the Forte framework, which consists of a general-purpose theorem-prover, ThmTac, on top of a symbolic trajectory evaluation based model-checking engine. The correctness of the circuit was formulated and decomposed to smaller, automatically model-checkable, statements in a pre/postcondition framework. The other key steps of the proof involved relating bit vectors to integer arithmetic and general arithmetic reasoning.