Theorem Proving for Verification (Invited Tutorial)

  • Authors:

  • John Harrison

  • Affiliations:

  • Intel Corporation, JF1-13, Hillsboro, USA OR 97124

  • Venue:
  • CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
  • Year:
  • 2008

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Abstract

There are numerous verification techniques in active use. Traditional testing and simulation usually only provide a limited guarantee, since they can seldom exercise all possible situations. Methods based on abstraction consciously simplify the problem to make its complete analysis tractable, but still do not normally completely verify the ultimate target. We will confine ourselves here to full formal verification techniques that can be used to prove complete correctness of a (model of a) system with respect to a formal specification. Roughly speaking, these methods model the system and specification in a logical formalism and then apply general methods to determine whether the formal expressions are valid, indicating correctness of the model with respect to the specification. Typical formalisms include:Propositional logic, a.k.a. Boolean algebraTemporal logic (CTL, LTL etc.)Quantifier-free combinations of first-order theoriesFull first-order logicHigher-order logic or first-order logic with arithmetic or set theoryThis list is organized approximately in order of increasing logical generality, with formalisms later in the list often subsuming earlier ones. But there is a price to be paid for this generality: deciding validity in the formalisms becomes successively more difficult.