Proof Engineering in the Large: Formal Verification of Pentium® 4 Floating-Point Divider

  • Authors:
  • Roope Kaivola;Katherine R. Kohatsu

  • Affiliations:
  • -;-

  • Venue:
  • CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
  • Year:
  • 2001

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Abstract

We examine the challenges presented by large-scale formal verification of industrial-size circuits, based on our experiences in verifying the class of all micro-operations executing on the floating-point division and square root unit of the Intel IA-32 Pentium®4 microprocessor. The verification methodology is based on combining human-guided mechanised theorem-proving with low-level steps verified by fully automated model-checking. A key observation in the work is the need to explicitly address the issues of proof design and proof engineering, i.e. the process of creating proofs and the craft of structuring and formulating them, as concerns on their own right.