Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of a superscalar execution unit
DAC '97 Proceedings of the 34th annual Design Automation Conference
Formal verification of content addressable memories using symbolic trajectory evaluation
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '98 Proceedings of the 35th annual Design Automation Conference
Combining theorem proving and trajectory evaluation in an industrial environment
DAC '98 Proceedings of the 35th annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Formal verification in hardware design: a survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Formal verification using parametric representations of Boolean constraints
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Reliable verification using symbolic simulation with scalar values
Proceedings of the 37th Annual Design Automation Conference
Formal verification of iterative algorithms in microprocessors
Proceedings of the 37th Annual Design Automation Conference
On Efficiently Producing Quality Tests forCustom Circuits in PowerPC™ Microprocessors
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Proceedings of the conference on Design, automation and test in Europe
The Formal Design of 1M-gate ASICs
Formal Methods in System Design - Special issue on formal methods for computer-added design
Handling special constructs in symbolic simulation
Proceedings of the 39th annual Design Automation Conference
Experience in Validation of PowerPCTM Microprocessor Embedded Arrays
Journal of Electronic Testing: Theory and Applications
Validating PowerPC Microprocessor Custom Memories
IEEE Design & Test
Practical Formal Verification in Microprocessor Design
IEEE Design & Test
Design and Development Paradigm for Industrial Formal Verification CAD Tools
IEEE Design & Test
Experience with Applying Formal Methods to Protocol Specification and System Architecture
Formal Methods in System Design
Formal Verification Successes at Motorola
Formal Methods in System Design
Verisym: Verifying Circuits by Symbolic Simulation
Formal Methods in System Design
LPAR '01 Proceedings of the Artificial Intelligence on Logic for Programming
Bit-Level Abstraction in the Verfication of Pipelined Microprocessors by Correspondence Checking
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
The Formal Design of 1M-gate ASICs
FMCAD '98 Proceedings of the Second International Conference on Formal Methods in Computer-Aided Design
A Methodology for Large-Scale Hardware Verification
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Combining Stream-Based and State-Based Verification Techniques
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Sequential Equivalence Checking by Symbolic Simulation
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Symbolic Simulation with Approximate Values
FMCAD '00 Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design
Abstraction by Symbolic Indexing Transformations
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Generalized Symbolic Trajectory Evaluation - Abstraction in Action
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving
TPHOLs '99 Proceedings of the 12th International Conference on Theorem Proving in Higher Order Logics
Divider Circuit Verification with Model Checking and Theorem Proving
TPHOLs '00 Proceedings of the 13th International Conference on Theorem Proving in Higher Order Logics
Xs are for Trajectory Evaluation, Booleans are for Theorem Proving
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Proof Engineering in the Large: Formal Verification of Pentium® 4 Floating-Point Divider
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
PROSPER - An Investigation into Software Architecture for Embedded Proof Engines
FroCoS '02 Proceedings of the 4th International Workshop on Frontiers of Combining Systems
Checking Safety Properties of Behavioral VHDL Descriptions by Abstract Interpretation
SAS '02 Proceedings of the 9th International Symposium on Static Analysis
The Mathematical Foundation fo Symbolic Trajectory Evaluation
CAV '99 Proceedings of the 11th International Conference on Computer Aided Verification
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Tradeoff Analysis For Producing High Quality Tests For Custom Circuits in PowerPCTM Microprocessors
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Introduction to generalized symbolic trajectory evaluation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Stimuli Generation with Late Binding of Values
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A Top-Down Methodology for Microprocessor Validation
IEEE Design & Test
Efficient Generation of Monitor Circuits for GSTE Assertion Graphs
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Improved symbolic simulation by functional-space decomposition
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Verification of Embedded Memory Systems using Efficient Memory Modeling
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Using 2-domain partitioned OBDD data structure in an enhanced symbolic simulator
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Enhanced symbolic simulation for efficient verification of embedded array systems
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Implication of assertion graphs in GSTE
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Partitioned model checking from software specifications
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Transition-by-transition FSM traversal for reachability analysis in bounded model checking
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Formal Methods in System Design
Journal of Embedded Computing - Real-Time and Embedded Computing Systems
Error Diagnosis in Equivalence Checking of High Performance Microprocessors
Electronic Notes in Theoretical Computer Science (ENTCS)
GSTE is partitioned model checking
Formal Methods in System Design
Computation of minimal counterexamples by using black box techniques and symbolic methods
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Optimizing automatic abstraction refinement for generalized symbolic trajectory evaluation
Proceedings of the 45th annual Design Automation Conference
Theorem Proving for Verification (Invited Tutorial)
CAV '08 Proceedings of the 20th international conference on Computer Aided Verification
Formal verification of hardware support for advanced encryption standard
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Word-level sequential memory abstraction for model checking
Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design
Enhancing bug hunting using high-level symbolic simulation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
CAV '09 Proceedings of the 21st International Conference on Computer Aided Verification
A Framework for Compositional Verification of Multi-valued Systems via Abstraction-Refinement
ATVA '09 Proceedings of the 7th International Symposium on Automated Technology for Verification and Analysis
SAT-based Induction for Temporal Safety Properties
Electronic Notes in Theoretical Computer Science (ENTCS)
Challenges for formal verification in industrial setting
FMICS'06/PDMC'06 Proceedings of the 11th international workshop, FMICS 2006 and 5th international workshop, PDMC conference on Formal methods: Applications and technology
CSCWD'06 Proceedings of the 10th international conference on Computer supported cooperative work in design III
A short survey of automated reasoning
AB'07 Proceedings of the 2nd international conference on Algebraic biology
3-valued circuit SAT for STE with automatic refinement
ATVA'07 Proceedings of the 5th international conference on Automated technology for verification and analysis
Efficient automatic STE refinement using responsibility
TACAS'08/ETAPS'08 Proceedings of the Theory and practice of software, 14th international conference on Tools and algorithms for the construction and analysis of systems
Selective state retention design using symbolic simulation
Proceedings of the Conference on Design, Automation and Test in Europe
A novel formalization of symbolic trajectory evaluation semantics in Isabelle/HOL
Theoretical Computer Science
Exploring structural symmetry automatically in symbolic trajectory evaluation
Formal Methods in System Design
On locally checkable properties
LPAR'06 Proceedings of the 13th international conference on Logic for Programming, Artificial Intelligence, and Reasoning
Explaining symbolic trajectory evaluation by giving it a faithful semantics
CSR'06 Proceedings of the First international computer science conference on Theory and Applications
Maximal models of assertion graph in GSTE
TAMC'06 Proceedings of the Third international conference on Theory and Applications of Models of Computation
FM'05 Proceedings of the 2005 international conference on Formal Methods
Combining several paradigms for circuit validation and verification
CASSIS'04 Proceedings of the 2004 international conference on Construction and Analysis of Safe, Secure, and Interoperable Smart Devices
Verification of an error correcting code by abstract interpretation
VMCAI'05 Proceedings of the 6th international conference on Verification, Model Checking, and Abstract Interpretation
SAT-based assistance in abstraction refinement for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Automatic refinement and vacuity detection for symbolic trajectory evaluation
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
Formal verification of pentium ® 4 components with symbolic simulation and inductive invariants
CAV'05 Proceedings of the 17th international conference on Computer Aided Verification
A new SAT-based algorithm for symbolic trajectory evaluation
CHARME'05 Proceedings of the 13 IFIP WG 10.5 international conference on Correct Hardware Design and Verification Methods
Approximate reachability with combined symbolic and ternary simulation
Proceedings of the International Conference on Formal Methods in Computer-Aided Design
An introduction to symbolic trajectory evaluation
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
BDD-Based hardware verification
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
Floating-Point verification using theorem proving
SFM'06 Proceedings of the 6th international conference on Formal Methods for the Design of Computer, Communication, and Software Systems
An integrated approach to verifying large circuits: a case study
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
Hardware dependability in the presence of soft errors
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
Combining theorem proving and symbolic trajectory evaluation in THM&STE
HVC'11 Proceedings of the 7th international Haifa Verification conference on Hardware and Software: verification and testing
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