Symbolic simulation—techniques and applications
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Formal verification by symbolic evaluation of partially-ordered trajectories
Formal Methods in System Design - Special issue on symbolic model checking
Logic verification methodology for PowerPC microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Formal verification of PowerPC arrays using symbolic trajectory evaluation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Formal verification of content addressable memories using symbolic trajectory evaluation
DAC '97 Proceedings of the 34th annual Design Automation Conference
Functional Testing of Semiconductor Random Access Memories
ACM Computing Surveys (CSUR)
Process-Aggravated Noise (PAN): New Validation and Test Problems
Proceedings of the IEEE International Test Conference on Test and Design Validity
Using Target Faults To Detect Non-Tartget Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
PowerPCTM Array Verification Methodology using Formal Techniques
Proceedings of the IEEE International Test Conference on Test and Design Validity
The PowerPC 603TM Microprocessor: An Array Built-In Self-Test Mechanism
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
VOSS - A Formal Hardware Verification System User''s Guide
VOSS - A Formal Hardware Verification System User''s Guide
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
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Test and validation of embedded array blocks remain asa major challenge in today's processor design environment.The difficulty comes from two folds. First, the sizes of thearrays are too large to be handled by the most sophisticatedsequential ATPG tools. On the other hand, the complextiming and control make it hard tomodel these arrays aswell-defined transparent blocks which combinational ATPGtools can understand. This paper describes a novel methodology for test and validation of complex array blocks inPowerPC RISC microprocessors. Unlike traditional ATPGmethods, our methodology uses formal techniques to functionally verify the arrays and then derive tests from theverification results. The superority of these tests over thetraditional ATPG tests will be discussed and shown at thetransistor level through experiments on various recent PowerPC array designs.