Fault analysis for computer memory systems and combinatorial logic networks
Fault analysis for computer memory systems and combinatorial logic networks
Efficient Testing of Optimal Time Adders
IEEE Transactions on Computers
TRAM: A Design Methodology for High-Performance, Easily Testable, Multimegabit RAMs
IEEE Transactions on Computers
Diagnosis and Repair of Memory with Coupling Faults
IEEE Transactions on Computers
An overview of deterministic functional RAM chip testing
ACM Computing Surveys (CSUR)
Increased Throughput for the Testing and Repair of RAMs with Redundancy
IEEE Transactions on Computers
Evaluation of FPGA resources for built-in self-test of programmable logic blocks
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Fault tolerant and BIST design of a FIFO cell
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
SRAM-Based FPGAs: Testing the Embedded RAM Modules
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Detection of Delay Faults in Memory Address Decoders
Journal of Electronic Testing: Theory and Applications
Proceedings of the conference on Design, automation and test in Europe
Efficient Tests for Realistic Faults in Dual-Port SRAMs
IEEE Transactions on Computers
CrossCheck: An Innovative Testability Solution
IEEE Design & Test
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests
Journal of Electronic Testing: Theory and Applications
A Specific Test Methodology for Symmetric SRAM-Based FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
SRAM-based FPGA's: testing the LUT/RAM modules
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Universal test complexity of field-programmable gate arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
Towards a Uniform Notation for Memory Tests
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Fast Optimal Robust Path Delay Fault Testable Adder
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Assessing SRAM test coverage for sub-micron CMOS technologies
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Different Experiments in Test Generation for XILINX FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Industrial Evaluation of Stress Combinations for March Tests applied to SRAMs
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Memory Fault Modeling Trends: A Case Study
Journal of Electronic Testing: Theory and Applications
Formal Methods in System Design
Test, diagnosis and fault simulation of embedded RAM modules in SRAM-based FPGAs
Microelectronic Engineering
Test set development for cache memory in modern microprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Fault modeling and test algorithm development for static random access memories
ITC'88 Proceedings of the 1988 international conference on Test: new frontiers in testing
Access time evaluation of fast static MOS memories
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
Fault simulation at the architectural level
ITC'84 Proceedings of the 1984 international test conference on The three faces of test: design, characterization, production
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