Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Field-programmable gate arrays
Field-programmable gate arrays
Testing of uncustomized segmented channel field programmable gate arrays
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Diagnosing programmable interconnect systems for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Evaluation of FPGA resources for built-in self-test of programmable logic blocks
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Functional Testing of Semiconductor Random Access Memories
ACM Computing Surveys (CSUR)
RAM-based FPGA's: a test approach for the configurable logic
Proceedings of the conference on Design, automation and test in Europe
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
Testing the Interconnect of RAM-Based FPGAs
IEEE Design & Test
A Test Methodology Applied to Cellular Logic Programmable Gate Arrays
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Fault Modeling and Test Generation for FPGAs
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
Universal test complexity of field-programmable gate arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA
ATS '97 Proceedings of the 6th Asian Test Symposium
Testing memory modules in SRAM-based configurable FPGAs
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
An approach for testing programmable/configurable field programmable gate arrays
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test of RAM-based FPGA: methodology and application to the interconnect
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Comments on "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories"
IEEE Transactions on Computers
An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories
IEEE Transactions on Computers
A March Test for Functional Faults in Semiconductor Random Access Memories
IEEE Transactions on Computers
Testing the configurable interconnect/logic interface of SRAM-based FPGA's
DATE '99 Proceedings of the conference on Design, automation and test in Europe
SRAM-Based FPGAs: Testing the Embedded RAM Modules
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Interconnect testing in cluster-based FPGA architectures
Proceedings of the 37th Annual Design Automation Conference
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Diagnosis of interconnect faults in cluster-based FPGA architectures
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Discussion on Test Pattern Generation for FPGA—Implemented Circuits
Journal of Electronic Testing: Theory and Applications
A Specific Test Methodology for Symmetric SRAM-Based FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Analyzing the Test Generation Problem for an Application-Oriented Test of FPGAs
ETW '00 Proceedings of the IEEE European Test Workshop
Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development
ITC '00 Proceedings of the 2000 IEEE International Test Conference
BIST-Based Detection and Diagnosis of Multiple Faults in FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Different Experiments in Test Generation for XILINX FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
IS-FPGA: A New Symmetric FPGA Architecture with Implicit SCAN
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Improving On-Line BIST-Based Diagnosis for Roving STARs
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Test, diagnosis and fault simulation of embedded RAM modules in SRAM-based FPGAs
Microelectronic Engineering
Resource-and-time-aware test strategy for configurable quaternary logic blocks
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Online BIST and BIST-based diagnosis of FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper addresses the problem of testing theLUT/RAM modules of configurable SRAM-based FPGAs usinga minimum number of test configurations. A model ofarchitecture for the LUT/RAM module with N inputs and 2Nmemory cells is proposed taking into account the LUT andRAM modes.Concerning the RAM mode, we demonstrate that a unique testconfiguration is required for a single module. The problem isshown equivalent to the test of a classical SRAM circuitallowing to use existing algorithms such as the march tests. Wealso propose a unique test configuration called pseudo shiftregister' for an mxm arrays of modules. In this configuration,the circuit operates as a shift register and an adapted version ofthe MATS++ algorithm called shifted MATS++' is described.Concerning the LUT mode, we use the concept of non-redundanttest that proposes to test in LUT mode the parts ofthe module not tested in RAM mode. Under this hypothesis, it isdemonstrated that the test of a single module as well as the testof an mxm array of modules require only 3 test configurations.Using our solution, the test of a complete array of mxmLUT/RAM modules requires 4 test configurations independentlyof the size of the array and of the modules.