Field-programmable gate arrays
Field-programmable gate arrays
Diagnosing programmable interconnect systems for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Evaluation of FPGA resources for built-in self-test of programmable logic blocks
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Testing the configurable interconnect/logic interface of SRAM-based FPGA's
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
Built-in self-test of FPGA interconnect
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ
ITC '98 Proceedings of the 1998 IEEE International Test Conference
SRAM-based FPGA's: testing the LUT/RAM modules
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Minimizing the Number of Test Configurations for Different FPGA Families
ATS '99 Proceedings of the 8th Asian Test Symposium
TOF: a tool for test pattern generation optimization of an FPGA application oriented test
ATS '00 Proceedings of the 9th Asian Test Symposium
A Test Methodology for Interconnect Structures of LUT-based FPGAs
ATS '96 Proceedings of the 5th Asian Test Symposium
Testing for the programming circuit of LUT-based FPGAs
ATS '97 Proceedings of the 6th Asian Test Symposium
Analyzing the Test Generation Problem for an Application-Oriented Test of FPGAs
ETW '00 Proceedings of the IEEE European Test Workshop
Testing memory modules in SRAM-based configurable FPGAs
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
An approach for testing programmable/configurable field programmable gate arrays
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test of RAM-based FPGA: methodology and application to the interconnect
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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This paper proposes a new and original FPGA architecturewith testability facilities. It is first demonstrated thatclassical FPGA architectures do not allow to efficientlyimplement sequential circuits with a SCAN chain. It isconsequently proposed to modify the architecture of classicalFPGAs in order to create an Implicit-Scan chain into theFPGA itself called Implicit Scan FPGA (IS-FPGA). Usingthis new FPGA architecture, any sequential circuitimplemented into the FPGA is 'implicitly scanned'. Anoriginal and optimal implementation of the proposedarchitecture is given with minimum area overhead andabsolutely no delay impact. Additionally the technique istransparent for the user as well as for the FPGA mappingtools. Finally, it is demonstrated that the Implicit-Scanconcept allow to over-scan' sequential circuits resulting inhighly testable circuits.