Test of RAM-based FPGA: methodology and application to the interconnect

Authors:
M. Renovell;J. Figueras;Y. Zorian
Affiliations:
-;-;-
Venue:
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Year:
1997

Citing 14
Cited 31

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Abstract

This paper proposes a methodology for testing RAM-based FPGA taking into account the configurability of such flexible devices. Two different approaches with different objectives are identified: the Manufacturing Test Procedure and the User Test Procedure. The proposed method is used to generate a Manufacturing Test Procedure targeting the Interconnect Structure of RAM-based FPGA. It is demonstrated that a set of only 3 Test Configurations called the Orthogonal, the Diagonal-1 and Diagonal-2 Test Configurations suffice to make 100% of the considered realistic fault set non-redundant. Then the test of each configuration is shown equivalent to the test of classical buses. The final proposed Manufacturing Test Procedure present a constant number of Test Configurations (3) and very short Test Sequences.