Evaluation of FPGA resources for built-in self-test of programmable logic blocks
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
Universal test complexity of field-programmable gate arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
A Test Methodology for Interconnect Structures of LUT-based FPGAs
ATS '96 Proceedings of the 5th Asian Test Symposium
On the diagnosis of programmable interconnect systems: Theory and application
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
An approach for testing programmable/configurable field programmable gate arrays
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test of RAM-based FPGA: methodology and application to the interconnect
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A New Diagnosis Approach for Short Faults in Interconnects
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Testing the configurable interconnect/logic interface of SRAM-based FPGA's
DATE '99 Proceedings of the conference on Design, automation and test in Europe
SRAM-Based FPGAs: Testing the Embedded RAM Modules
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
Interconnect testing in cluster-based FPGA architectures
Proceedings of the 37th Annual Design Automation Conference
An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family
Journal of Electronic Testing: Theory and Applications - special issue on the European test workshop 1999
Testing the Local Interconnect Resources of SRAM-Based FPGA's
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
FPGA test time reduction through a novel interconnect testing scheme
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Diagnosis of interconnect faults in cluster-based FPGA architectures
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Specific Test Methodology for Symmetric SRAM-Based FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
SRAM-based FPGA's: testing the LUT/RAM modules
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development
ITC '00 Proceedings of the 2000 IEEE International Test Conference
NOVEL TECHNIQUE FOR BUILT-IN SELF-TEST OF FPGA INTERCONNECTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
BIST-Based Detection and Diagnosis of Multiple Faults in FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Different Experiments in Test Generation for XILINX FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
BIST-Based Delay Path Testing in FPGA Architectures
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Improving On-Line BIST-Based Diagnosis for Roving STARs
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Testing strategies for networks on chip
Networks on chip
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
A novel FPGA local interconnect test scheme and automatic TC derivation/generation
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Fault tolerance of switch blocks and switch block arrays in FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults
Journal of Electronic Testing: Theory and Applications
A Self-Test of Dynamically Reconfigurable Processors with Test Frames
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Online BIST and BIST-based diagnosis of FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability and availability in reconfigurable computing: a basis for a common solution
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Programmable logic in the form of field-programmable gate arrays has become a widely accepted design approach for low- and medium-volume computing applications. Low development costs and inherent functional flexibility have spurred the spectacular growth of this technology. FPGAs are regular structures of logic modules communicating via an interconnect architecture of lines and switches. Users program the logic modules and interconnect structures to perform particular functions and realize the FPGA's global function.Manufacturers provide programmability in their FPGA architectures in various ways. They may use RAM to store configuration information, EPROM switches based on FAMOS (floating-gate avalanche-injection metal oxide semiconductor) transistors and fuses, or antifuses that permanently open or close connections. Of these alternatives, we have focused our work on RAM-based FPGAs. Their simplicity and flexibility for user changes in the field make this type of FPGA a very popular choice among designers. The architecture and design of these devices have been widely investigated during the last decade, but their test challenges have received less attention. Only recently have researchers addressed the problem of testing after manufacture-in other words, before user programming of specific functions. Testing before programming presents a wide spectrum of problems, for which a number of researchers have proposed innovative solutions.Testing an FPGA chip poses a challenging problem for test engineers. It requires implementing various configurations (programmings) of the FPGA. But changing configurations incurs reprogramming costs. So the question arises: How can we determine the minimum number of test configurations and corresponding vector test sequences that will cover all the faults of an FPGA's structural fault model? Dealing with this question in an earlier work, we proposed a general methodology for test configuration and test pattern generation. 5 Here, we apply this methodology to the interconnect structure. We propose a manufacturing test procedure for RAM- based FPGA interconnect structures.