Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
On generating all maximal independent sets
Information Processing Letters
Universal switch-module design for symmetric-array-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
More wires and fewer LUTs: a design methodology for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Interconnect testing in cluster-based FPGA architectures
Proceedings of the 37th Annual Design Automation Conference
Introduction to Algorithms
Testing the Interconnect of RAM-Based FPGAs
IEEE Design & Test
Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Built-in self-test of FPGA interconnect
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Testing the Logic Cells and Interconnect Resources for FPGAs
ATS '99 Proceedings of the 8th Asian Test Symposium
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
On the diagnosis of programmable interconnect systems: Theory and application
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Automatic Configuration Generation for FPGA Interconnect Testing
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
NOVEL TECHNIQUE FOR BUILT-IN SELF-TEST OF FPGA INTERCONNECTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Application-Dependent Testing of FPGA Interconnects
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Column-Based Precompiled Configuration Techniques for FPGA
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Routability and Fault Tolerance of FPGA Interconnect Architectures
ITC '04 Proceedings of the International Test Conference on International Test Conference
Digital Signal Processing
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A new application-independent approach for evaluating the fault tolerance of field-programmable gate-array (FPGA) interconnect structures is presented. Signal routing in the presence of faulty resources at switch block and FPGA levels is analyzed; this problem is directly related to the fault tolerance of FPGA interconnects for testing and reconfiguration at manufacturing and run-time applications. Two criteria are proposed and used as figure-of-merit for evaluating different FPGA interconnect architectures. The proposed approach is based on the number of available paths between pairs of end points and the probability to establish a one-to-one mapping between all input and output end points. A probabilistic approach is also presented to evaluate the fault-tolerant routing of the entire FPGA by connecting switch blocks in chains, as required for testing and to account for the input-output (I/O) pin restrictions of an FPGA chip. All possible interconnect faults for programmable switches and wiring channels are considered in the fault model. The proposed method is applicable to arbitrary switch block structures. Experimental results on commercial as well as academic designed FPGAs are presented and analyzed.