More wires and fewer LUTs: a design methodology for FPGAs

Authors:
Atsushi Takahara;Toshiaki Miyazaki;Takahiro Murooka;Masaru Katayama;Kazuhiro Hayashi;Akihiro Tsutsui;Takaki Ichimori;Ken-nosuke Fukami
Affiliations:
NTT Optical Network Systems Laboratories;NTT Optical Network Systems Laboratories;NTT Optical Network Systems Laboratories;NTT Optical Network Systems Laboratories;NTT Optical Network Systems Laboratories;NTT Optical Network Systems Laboratories;NTT Network Service Systems Laboratories;NTT Science and Core Technology Laboratory Group
Venue:
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Year:
1998

Citing 7
Cited 6

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Abstract

In designing FPGAs, it is important to achiev e a good balance bet w een the number of logic blocks, suc h has Look-Up Tables (LUTs), and wiring resources. It is difficult to find an optimal solution. In this paper, w e presen t an FPGA design methodology to efficiently find well-balanced FPGA architectures. The method covers all aspects of FPGA development from the architecture-decision process to physical implementation. It has been used to develop a new FPGA that can implement circuits that are twice as large as those implementable with the previous version but with half the number of logic blocks. This indicates that the methodology is effectiv e in dev eloping well-balanced FPGAs.