More wires and fewer LUTs: a design methodology for FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Logic Testing of Bridging Faults in CMOS Integrated Circuits
IEEE Transactions on Computers
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Interconnect testing in cluster-based FPGA architectures
Proceedings of the 37th Annual Design Automation Conference
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
IS-FPGA: a new symmetric FPGA architecture with implicit scan
Proceedings of the IEEE International Test Conference 2001
Built-in self-test of FPGA interconnect
ITC '98 Proceedings of the 1998 IEEE International Test Conference
BIST-based delay path testing in FPGA architectures
Proceedings of the IEEE International Test Conference 2001
Testing the Logic Cells and Interconnect Resources for FPGAs
ATS '99 Proceedings of the 8th Asian Test Symposium
A Test Methodology for Interconnect Structures of LUT-based FPGAs
ATS '96 Proceedings of the 5th Asian Test Symposium
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
On the diagnosis of programmable interconnect systems: Theory and application
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Automatic Configuration Generation for FPGA Interconnect Testing
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
NOVEL TECHNIQUE FOR BUILT-IN SELF-TEST OF FPGA INTERCONNECTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
BIST-Based Detection and Diagnosis of Multiple Faults in FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
WHICH CONCURRENT ERROR DETECTION SCHEME TO CHOOSE?
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Different Experiments in Test Generation for XILINX FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Application-Dependent Testing of FPGA Interconnects
DFT '03 Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Application-Specific Bridging Fault Testing of FPGAs
Journal of Electronic Testing: Theory and Applications
Column-Based Precompiled Configuration Techniques for FPGA
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
New performance-driven FPGA routing algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
BISM: built-in self map for hybrid crossbar nano-architectures
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Fine grain faults diagnosis of FPGA interconnect
Microprocessors & Microsystems
On-line testing of permanent radiation effects in reconfigurable systems
Proceedings of the Conference on Design, Automation and Test in Europe
GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
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Testing techniques for interconnect and logic resources of an arbitrary design implemented into a field-programmable gate array (FPGA) are presented. The target fault list includes all stuck-at, open, and pair-wise bridging faults in the mapped design. For interconnect testing, only the configuration of the used logic blocks is changed, and the structure of the design remains unchanged. For logic block testing, the configuration of used logic resources remains unchanged, while the interconnect configuration and unused logic resources are modified. Logic testing is performed in only one test configuration whereas interconnect testing is done in a logarithmic number of test configurations. This approach is able to achieve 100% fault coverage.