Test and diagnosis of fault logic blocks in FPGAs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficiently supporting fault-tolerance in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays
IEEE Transactions on Computers
An Approach for Detecting Multiple Faulty FPGA Logic Blocks
IEEE Transactions on Computers
Novel technique for testing FPGAs
Proceedings of the conference on Design, automation and test in Europe
Using embedded FPGAs for SoC yield improvement
Proceedings of the 39th annual Design Automation Conference
IEEE Design & Test
Self-Testing of Linear Segments in User-Programmed FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPFAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
On the Set of Target Path Delay Faults in Sequential Subcircuits of LUT-based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Built-in self-test of FPGA interconnect
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Detection of bridging faults in logic resources of configurable FPGAs using I_DDQ
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Using satisfiability in application-dependent testing of FPGA interconnects
Proceedings of the 40th annual Design Automation Conference
Fault Scanner for Reconfigurable Logic
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Tunable Fault Tolerance for Runtime Reconfigurable Architectures
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development
ITC '00 Proceedings of the 2000 IEEE International Test Conference
BIST-Based Detection and Diagnosis of Multiple Faults in FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
ON-LINE TESTABLE LOGIC DESIGN FOR FPGA IMPLEMENTATION
ITC '97 Proceedings of the 1997 IEEE International Test Conference
BIST-Based Diagnostics of FPGA Logic Blocks
ITC '97 Proceedings of the 1997 IEEE International Test Conference
Self-Testing of FPGA Delay Faults in the System Environment
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
Improving On-Line BIST-Based Diagnosis for Roving STARs
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
BIST-Based Delay-Fault Testing in FPGAs
Journal of Electronic Testing: Theory and Applications
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Application-Specific Bridging Fault Testing of FPGAs
Journal of Electronic Testing: Theory and Applications
Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults
Proceedings of the conference on Design, automation and test in Europe: Proceedings
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs
Journal of Electronic Testing: Theory and Applications
Application-dependent testing of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SEU mitigation for sram-based fpgas through dynamic partial reconfiguration
Proceedings of the 17th ACM Great Lakes symposium on VLSI
A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology
Journal of Electronic Testing: Theory and Applications
Built-in Self-test and Defect Tolerance in Molecular Electronics-based Nanofabrics
Journal of Electronic Testing: Theory and Applications
SCT: A novel approach for testing and configuring nanoscale devices
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A Self-Test of Dynamically Reconfigurable Processors with Test Frames
IEICE - Transactions on Information and Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Online BIST and BIST-based diagnosis of FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability and availability in reconfigurable computing: a basis for a common solution
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Roberts: reconfigurable platform for benchmarking real-time systems
ACM SIGARCH Computer Architecture News - ACM SIGARCH Computer Architecture News/HEART '12
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We present a new approach for Field Programmable Gate Array (FPGA) testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without any area overhead or performance penalties to the system function implemented by the FPGA. Our approach is applicable to all levels of testing, achieves maximal fault coverage, and all tests are applied at-speed. We describe the BIST architecture used to test all the programmable logic blocks in an FPGA and the configurations required to implement our approach using a commercial FPGA. We also discuss implementation problems caused by CAD tool limitations and limited architectural resources, and we describe techniques which overcome these limitations.