Testing configurable LUT-based FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Proceedings of the 37th Annual Design Automation Conference
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Architecture and CAD for Deep-Submicron FPGAs
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ITC '98 Proceedings of the 1998 IEEE International Test Conference
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Proceedings of the IEEE International Test Conference 2001
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ETW '00 Proceedings of the IEEE European Test Workshop
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VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
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ITC '00 Proceedings of the 2000 IEEE International Test Conference
BIST-Based Delay-Fault Testing in FPGAs
IOLTW '02 Proceedings of the Proceedings of The Eighth IEEE International On-Line Testing Workshop (IOLTW'02)
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Requirements for Delay Testing of Look-Up Tables in SRAM-Based FPGAs
ETW '03 Proceedings of the 8th IEEE European Test Workshop
High Quality TPG for Delay Faults in Look-Up Tables of FPGAs
DELTA '04 Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications
Bridging fault detection in cluster based FPGA by using Muller C element
Computers and Electrical Engineering
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The objective of this paper is to propose a BIST scheme enabling the test of delay faults in all the Look-Up Tables (LUTs) of FPGA SRAMs, in a Manufacturing context. The BIST scheme does not consume any area overhead and can be removed from the device after the test thus, allowing the use of the whole circuit by the user. The structure we propose is composed of a simple test pattern generator, an error detector and a chain of LUTs. The chain of LUTs is formed alternatively by a LUT and a flip---flop. By using such a chain, the test of all delay faults in every LUT is enabled. In this paper, we develop an experiment based on the implantation of our BIST architecture in a Virtex FPGA from Xilinx. The purpose of this experiment is to show the feasibility of our solution. As a result, one important issue from this solution is its ability to detect the "smallest" delay faults in the LUTs, i.e. the smallest delays that can be observed on a LUT output.