EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
FPGA Bridging Fault Detection and Location via Differential I{DDQ}
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A BIST Approach for Testing FPGAs Using JBITS
FCCM '05 Proceedings of the 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs
Journal of Electronic Testing: Theory and Applications
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults
Journal of Electronic Testing: Theory and Applications
IOLTS '08 Proceedings of the 2008 14th IEEE International On-Line Testing Symposium
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
An embedded, FPGA-based computer graphics coprocessor with native geometric algebra support
Integration, the VLSI Journal
A compact AES core with on-line error-detection for FPGA applications with modest hardware resources
Microprocessors & Microsystems
A Single-Configuration Method for Application-Dependent Testing of SRAM-based FPGA Interconnects
ATS '11 Proceedings of the 2011 Asian Test Symposium
Self-checking test circuits for latches and flip-flops
IOLTS '11 Proceedings of the 2011 IEEE 17th International On-Line Testing Symposium
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this work, we propose a testing technique for detecting single stuck-at and bridging faults in the interconnects of the cluster based FPGA. The presence of the feedback-bridging fault, race and glitch poses major challenges to the detection of the fault. The feedback bridging fault has a high ingredient of delay dependent properties due to the variation of the feedback path delay. So we have exploited the concept of asynchronous logic in order to detect the fault. We configure the block under test (BUT) with a pseudo delay independent asynchronous element known as Muller C element. The novelty of this scheme lies in the fact that, it can detect the stuck-at and bridging fault including the feedback bridging fault by a single test configuration. The Xilinx Jbits 3.0 API (Application Program Interface) is used to implement the BISTER (Built-in-self-tester) structure in the FPGA. In comparison to the traditional FPGA development tool (ISE), 'Jbits' gives more controllability for which the partial run time reconfiguration of the FPGA is easily achieved.