Using embedded FPGAs for SoC yield improvement
Proceedings of the 39th annual Design Automation Conference
BIST-Based Delay-Fault Testing in FPGAs
Journal of Electronic Testing: Theory and Applications
A Hardware Artificial Immune System and Embryonic Array for Fault Tolerant Systems
Genetic Programming and Evolvable Machines
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fault tolerance of switch blocks and switch block arrays in FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Online fault tolerance for FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware based genetic evolution of self-adaptive arbitrary response FIR filters
Applied Soft Computing
Autonomic fault-handling and refurbishment using throughput-driven assessment
Applied Soft Computing
Online BIST and BIST-based diagnosis of FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microprocessors & Microsystems
Self-healing reconfigurable logic using autonomous group testing
Microprocessors & Microsystems
Proceedings of the Conference on Design, Automation and Test in Europe
Bridging fault detection in cluster based FPGA by using Muller C element
Computers and Electrical Engineering
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Abstract: We present an integrated approach to on-line FPGA testing, diagnosis, and fault-tolerance, to be used in high-reliability and high-availability hardware. The testing and diagnostic process takes place in Self-Testing AReas (STARs) of the FPGA, without disturbing the normal system operation. The entire chip is tested by roving the STARs across the FPGA. Our approach guarantees complete testing of both logic cells and interconnect with maximum diagnostic resolution. Our multi-level fault-tolerant technique allows using partially defective logic and routing resources for normal operation, providing longer mission life in the presence of faults. In addition, our dynamic fault-tolerant method ensures that spare resources are always present in the neighborhood of the located fault, thus simplifying fault-bypassing. Our complete method has been successfully implemented and demonstrated on the ORCA 2CA series FPGAs from Lucent Technologies.