IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays
IEEE Transactions on Computers
Tolerating operational faults in cluster-based FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Highly Fault-Tolerant FPGA Processor by Degrading Strategy
PRDC '02 Proceedings of the 2002 Pacific Rim International Symposium on Dependable Computing
BIST-Based Detection and Diagnosis of Multiple Faults in FPGAs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
EH '01 Proceedings of the The 3rd NASA/DoD Workshop on Evolvable Hardware
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A survey of fault tolerant methodologies for FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-Line Self-Healing of Circuits Implemented on Reconfigurable FPGAs
IOLTS '07 Proceedings of the 13th IEEE International On-Line Testing Symposium
A Regular Layout for Parallel Adders
IEEE Transactions on Computers
Online fault tolerance for FPGA logic blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking
Proceedings of the conference on Design, automation and test in Europe
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
IEEE Transactions on Computers
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This paper examines fault tolerant adder designs implemented on FPGAs which are inspired by the methods of modular redundancy, roving, and gradual degradation. A parallel-prefix adder based upon the Kogge-Stone configuration is compared with the simple ripple carry adder (RCA) design. The Kogge-Stone design utilizes a sparse carry tree complemented by several smaller RCAs. Additional RCAs are inserted into the design to allow fault tolerance to be achieved using the established methods of roving and gradual degradation. A triple modular redundant ripple carry adder (TMR-RCA) is used as a point of reference. Simulation and experimental measurements on a Xilinx Spartan 3E FPGA platform are carried out. The TMR-RCA is found to have the best delay performance and most efficient resource utilization for an FPGA fault-tolerant implementation due to the simplicity of the approach and the use of the fast-carry chain. However, the superior performance of the carry-tree adder over an RCA in a VLSI implementation makes this proposed approach attractive for ASIC designs.