Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
Proceedings of the 1st conference on Computing frontiers
On the Evaluation of SEU Sensitiveness in SRAM-Based FPGAs
IOLTS '04 Proceedings of the International On-Line Testing Symposium, 10th IEEE
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs
IEEE Transactions on Computers
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs
Journal of Electronic Testing: Theory and Applications
SEU mitigation for sram-based fpgas through dynamic partial reconfiguration
Proceedings of the 17th ACM Great Lakes symposium on VLSI
SCS '06 Proceedings of the eleventh Australian workshop on Safety critical systems and software - Volume 69
Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications
Proceedings of the 21st annual symposium on Integrated circuits and system design
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
A New Timing Driven Placement Algorithm for Dependable Circuits on SRAM-based FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A study of the single event effects impact on functional mapping within flash-based FPGAs
Proceedings of the Conference on Design, Automation and Test in Europe
A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes
Microelectronics Journal
Review: A survey of memory error correcting techniques for improved reliability
Journal of Network and Computer Applications
Journal of Electronic Testing: Theory and Applications
Mitigation of soft errors in SRAM-based FPGAs using CAD tools
Computers and Electrical Engineering
Low-power soft error hardened latch
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A fault injection analysis of Linux operating on an FPGA-embedded platform
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Self-healing reconfigurable logic using autonomous group testing
Microprocessors & Microsystems
A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design
Microelectronics Journal
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Triple Modular Redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA. However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections between signals from distinct redundant logic parts, which can generate an error in the output. This paper investigates the optimal design of the TMR logic (e.g., by cleverly inserting voters) to ensure robustness. Four different versions of a TMR digital filter were analyzed by fault injection. Faults were randomly inserted straight into the bitstream of the FPGA. The experimental results presented in this paper demonstrate that the number and placement of voters in the TMR design can directly affect the fault tolerance, ranging from 4.03% to 0.98% the number of upsets in the routing able to cause an error in the TMR circuit.