IEEE Transactions on Computers
Byte-Oriented Error-Correcting Codes for Semiconductor Memory Systems
IEEE Transactions on Computers
Area efficient methods to increase the reliability of combinatorial circuits
Proceedings of the 6th Annual Symposium on Theoretical Aspects of Computer Science on STACS 89
Symbol Error-Correcting Codes for Computer Memory Systems
IEEE Transactions on Computers
IBM experiments in soft fails in computer electronics (1978–1994)
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
Accelerated testing for cosmic soft-error rate
IBM Journal of Research and Development - Special issue: terrestrial cosmic rays and soft errors
A Class of Error Control Codes for Byte Organized Memory Systems -SbEC-(Sb+S)ED Codes-
IEEE Transactions on Computers
Increasing relevance of memory hardware errors: a case for recoverable programming models
EW 9 Proceedings of the 9th workshop on ACM SIGOPS European workshop: beyond the PC: new challenges for the operating system
Transient Fault Tolerance in Digital Systems
IEEE Micro
Design Considerations in Boeing 777 Fly-By-Wire Computers
HASE '98 The 3rd IEEE International Symposium on High-Assurance Systems Engineering
Area Efficient Methods to Increase the Reliability of Circuits
Data Structures and Efficient Algorithms, Final Report on the DFG Special Joint Initiative
Soft-Error Detection through Software Fault-Tolerance Techniques
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor
Proceedings of the 31st annual international symposium on Computer architecture
On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Design and Evaluation of Hybrid Fault-Detection Systems
Proceedings of the 32nd annual international symposium on Computer Architecture
CIT '06 Proceedings of the Sixth IEEE International Conference on Computer and Information Technology
Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique
DFT '06 Proceedings of the 21st IEEE International Symposium on on Defect and Fault-Tolerance in VLSI Systems
Error-Correcting Codes with Byte Error-Detection Capability
IEEE Transactions on Computers
System RAS implications of DRAM soft errors
IBM Journal of Research and Development
Split-Precharge Differential Noise-Immune Threshold Logic Gate (SPD-NTL)
IWANN '03 Proceedings of the 7th International Work-Conference on Artificial and Natural Neural Networks: Part II: Artificial Neural Nets Problem Solving Methods
Computation in the presence of noise
IBM Journal of Research and Development
IBM Journal of Research and Development
A class of optimal minimum odd-weight-column SEC-DED codes
IBM Journal of Research and Development
Modeling soft errors for data caches and alleviating their effects on data reliability
Microprocessors & Microsystems
Majority multiplexing-economical redundant fault-tolerant designs for nanoarchitectures
IEEE Transactions on Nanotechnology
Efficient erasure correcting codes
IEEE Transactions on Information Theory
On the complexity of decoding Reed-Solomon codes (Corresp.)
IEEE Transactions on Information Theory
On the complexity of decoding Goppa codes (Corresp.)
IEEE Transactions on Information Theory
Optimal codes for correcting single errors and detecting adjacent errors
IEEE Transactions on Information Theory
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Computer systems failure due to hard or soft memory errors is very common. Hard errors are caused due to any permanent fault in the memory chips whereas soft errors in memory chips, generally transients or intermittent in nature, are caused due to alpha particles or cosmic rays. Non-critical systems may not require serious attention for such failures where simple, cost-effective, little-overhead techniques may be considered enough. However, semi/fully critical systems do require a careful treatment, keeping aside all other factors, but the reliability and serviceability during the intended period of time. A number of monolithic and hybrid techniques have been developed over the years. This paper aims to expose the concerns related to increasing memory and logic errors as an off-shoot due to the advancement in technologies. A survey is presented regarding the techniques being used to deal with such errors.