An Algebraic Model of Fault-Masking Logic Circuits
IEEE Transactions on Computers
Error-Control Techniques for Logic Processors
IEEE Transactions on Computers
Review: A survey of memory error correcting techniques for improved reliability
Journal of Network and Computer Applications
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The behavior of a system consisting of a preliminary coder, an unreliable computer, and a decoder is investigated. Coding input blocks of k binary digits into output blocks of nk binary digits, it is shown that a simple combinational computer which can take the and or or of k or more input blocks can only be made arbitrarily reliable by making n/k arbitrarily large, so that the capacity for computation, in an information theory coding sense, is zero. Incomplete results for a single and or or circuit give the same result if the output gives no information about the inputs except for the information about their and or or; if this is not demanded, then for n2k, reliable computation through noisy computing circuits is possible, but the computing is done in the decoder.