Error Coding for Arithmetic Processors
Error Coding for Arithmetic Processors
Introduction to VLSI Systems
Error Correction in Redundant Residue Number Systems
IEEE Transactions on Computers
Design of Two-Level Fault-Tolerant Networks
IEEE Transactions on Computers
Acceptable Testing of VLSI Components Which Contain Error Correctors
IEEE Transactions on Computers
The Concept of Coverage and Its Effect on the Reliability Model of a Repairable System
IEEE Transactions on Computers
Design of a Self-Checking Microprogram Control
IEEE Transactions on Computers
Design of Totally Self-Checking Check Circuits for m-Out-of-n Codes
IEEE Transactions on Computers
A Combinatorial Solution to the Reliability of Interwoven Redundant Logic Networks
IEEE Transactions on Computers
Fault Tolerance of a General Purpose Computer Implemented by Very Large Scale Integration
IEEE Transactions on Computers
A Highly Efficient Redundancy Scheme: Self-Purging Redundancy
IEEE Transactions on Computers
IEEE Transactions on Computers
Reliability Modeling for Fault-Tolerant Computers
IEEE Transactions on Computers
Error-Control Techniques for Logic Processors
IEEE Transactions on Computers
Fault Detection Capabilities of Alternating Logic
IEEE Transactions on Computers
Redundancy by Coding Versus Redundancy by Replication for Failure-Tolerant Sequential Circuits
IEEE Transactions on Computers
Arithmetic Algorithms for Error-Coded Operands
IEEE Transactions on Computers
Fault-Tolerant Computers Using ``Dotted Logic'' Redundancy Techniques
IEEE Transactions on Computers
On codes for checking logical operations
IBM Journal of Research and Development
IBM Journal of Research and Development
Computation in the presence of noise
IBM Journal of Research and Development
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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In this paper, an algebraic model of fault-masking logic (FML) circuits, assuming bitwise logical operations and a separate single-valued coding system is presented. From this model, the neccessary and sufficient conditions to construct FML circuits are derived, and the error-propagating and error-correcting characteristics of such FML circuits are defined in terms of a Boolean vector algebra and a syndrome-like function. The capabilities and limitations of FML circuits are characterized and several constructive techniques are explored. Optimum FML constructions are developed for correcting a maximum number of faults in a minimum number of logic levels for simple logic structures. For complex logic structures, these constructions apply but it is not known if they are optimum. In addition, the enhancement of FML circuits with fault-detecting capabilities is developed in the event that the error-correcting capabilities of FML circuits should be exceeded.