Reliability modeling techniques for self-repairing computer systems
ACM '69 Proceedings of the 1969 24th national conference
Design of fault-tolerant computers
AFIPS '67 (Fall) Proceedings of the November 14-16, 1967, fall joint computer conference
AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
Design of Two-Level Fault-Tolerant Networks
IEEE Transactions on Computers
Realization of Fault-Tolerant Machines Linear Code Application
IEEE Transactions on Computers
Fail-Safe Asynchronous Sequential Machines
IEEE Transactions on Computers
Fail-Safe Asynchronous Machines with Multiple-Input Changes
IEEE Transactions on Computers
An Algebraic Model of Fault-Masking Logic Circuits
IEEE Transactions on Computers
Realization of fault-tolerant and Fail-Safe sequential machines
IEEE Transactions on Computers
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A new redundancy technique termed dotted logic is presented. Critical input errors are eliminated by joining together the output of NAND gates and NOR gates. The remaining subcritical errors are corrected by introducing redundant inputs to each logic element. Two different schemes, dotted alternating and dotted identical, are described and compared with existing error-correcting techniques. It is shown that these new methods have several advantages over quadded or triple modular redundancy (TMR) networks. In addition to correcting single faults, dotted schemes are easily extended to cover multiple faults. Methods for initial failure determinations for dotted schemes are proposed. Finally, it is shown that a network consisting of complex function elements can be made more reliable by dotting.