Design of fault-tolerant computers
AFIPS '67 (Fall) Proceedings of the November 14-16, 1967, fall joint computer conference
A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures
IEEE Transactions on Computers
Figure of Merit for Fault-Tolerant Space Computers
IEEE Transactions on Computers
Switch Complexity in Systems with Hybrid Redundancy
IEEE Transactions on Computers
An Iterative Cell Switch Design for Hybrid Redundancy
IEEE Transactions on Computers
Shared Logic Realizations of Dynamically Self-Checked and Fault-Tolerant Logic
IEEE Transactions on Computers
Reliability Modeling of Compensating Module Failures in Majority Voted Redundancy
IEEE Transactions on Computers
Synchronization and Matching in Redundant Systems
IEEE Transactions on Computers
Performance-Related Reliability Measures for Computing Systems
IEEE Transactions on Computers
A Highly Efficient Redundancy Scheme: Self-Purging Redundancy
IEEE Transactions on Computers
Computation-Based Reliability Analysis
IEEE Transactions on Computers
IEEE Transactions on Computers
Reliability Analysis of Systems with Concurrent Error Detection
IEEE Transactions on Computers
On Evaluating the Performability of Degradable Computing Systems
IEEE Transactions on Computers
A Unified Reliability Model for Fault-Tolerant Computers
IEEE Transactions on Computers
Ultrahigh Reliability Prediction for Fault-Tolerant Computer Systems
IEEE Transactions on Computers
A framework for hardware-software tradeoffs in the design of fault-tolerant computers
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
AFIPS '72 (Fall, part I) Proceedings of the December 5-7, 1972, fall joint computer conference, part I
An overview of fault-tolerant digital system architecture
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
Modular redundancy without voters decreases complexity of restoring organ
AFIPS '77 Proceedings of the June 13-16, 1977, national computer conference
A Reliability Model for Various Switch Designs in Hybrid Redundancy
IEEE Transactions on Computers
Fault-Tolerant Computers Using ``Dotted Logic'' Redundancy Techniques
IEEE Transactions on Computers
Fault-tolerant synthesis using non-uniform redundancy
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Optimal design of hybrid fault-tolerant computer systems
Mathematical and Computer Modelling: An International Journal
Selectively fortifying reconfigurable computing device to achieve higher error resilience
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
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The objective to attain fault-tolerant computing has been gaining an increasing amount of attention in the past several years. A digital computer is said to be fault-tolerant when it can carry out its programs correctly in the presence of logic faults, which are defined as any deviations of the logic variables in a computer from the design values. Faults can be either of transient or permanent duration. Their principal causes are: (1) component failures (either permanent or intermitent) in the circuits of the computer, and (2) external interference with the functioning of the computer, such as electric noise or transient variations in power supplies, electromagnetic interference, etc.