Optimal design of hybrid fault-tolerant computer systems

Authors:
Hoang Pham
Affiliations:
EG&G Idaho National Engineering Laboratory Idaho Falls, Idaho 83415, USA U.S.A.
Venue:
Mathematical and Computer Modelling: An International Journal
Year:
1992

Citing 5
Cited 0

Fault tolerant and fault testable hardware design

Fault tolerant and fault testable hardware design
On Reliability Modeling and Analysis of Ultrareliable Fault-Tolerant Digital Systems

IEEE Transactions on Computers
Design of fault-tolerant computers

AFIPS '67 (Fall) Proceedings of the November 14-16, 1967, fall joint computer conference
Reliability analysis and architecture of a hybrid-redundant digital system: generalized triple modular redundancy with self-repair

AFIPS '70 (Spring) Proceedings of the May 5-7, 1970, spring joint computer conference
Reliability improvement through redundancy at various system levels

IBM Journal of Research and Development

Quantified Score

Hi-index	0.98

Visualization

Abstract

In many critical applications of digital systems, fault tolerance has been an essential architectural attribute for achieving high reliability. We address the problem of designing an optimal hybrid fault-tolerant computer system. The designer of a system is always confronted with the problem of trading off reliability vs. cost. On the one hand, it is essential to provide for each vital module of the system as many spare units as possible in order to ensure high reliability. On the other hand, it is essential not to have an excessively costly, heavy or bulky system. In this paper, we determine the optimal number of spare units which minimizes the average total system cost. A numerical example is provided to illustrate the methods.